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PCM6260Q1EVM-PDK: PCM6260Q1 TDM6 Output Configuration Issue - PLL Lock Error

Rajul Bhambay
Prodigy 280 points
Part Number: PCM6260Q1EVM-PDK

Tool/software:

I am currently trying to output TDM6 signal from PCM6260Q1 via DOUT1 pin and i have used the external ASI configuration. Here are the details:
- TDM6 output requirements:
* BCLK: 2.048 MHz
* FSYNC: 16 kHz
* 6 channels
* 16-bit per channel
* MCLK: 8.192 MHz

Hardware Setup:
- PCM6260Q1EVM-PDK
- External clock source connected to J7:
* MCLK
* BCLK
* FSYNC
* DOUT1 (output)

Software Configuration:
- PPC3 GUI settings:
* TDM protocol
* 16-bit word length
* Channels mapped to slots 0-5
* Auto Clock Configuration enabled

Current Status:
1. Random pattern observed on DOUT1
2. PLL Lock showing red error in PPC3 GUI

Questions:
1. What are the correct clock requirements for this TDM6 configuration?
2. How to resolve PLL Lock error?
3. Are there specific register settings needed beyond GUI configuration?
4. What's the recommended troubleshooting sequence for TDM output verification?

  • 0
    TI__Mastermind 30641 points

    Hi Rajul,

    In general when you use  the dedicated  GUI for a device , then the GUI should configure the registers for you . 

    From your description,  you are providing the clks externally (Slave mode) so I would check my clks set up for TDM.

    BCLK= # of Ch.  *  Ch depth  * Fs   

    according to your post, you have 6 Ch, 16bit, and 16kHz , that requires a BCK of 1.54MHz for correct set up and you are using BCLK of 2.048 MHz

    You are using MCLK= 8.192KHz  so it is 512x Fs ( register  0x16  MCLK_RATIO_SEL[2:0] can be checked to verify this)

    Please see if modifying BCK would fix the issue, if not,  we will look into it further more.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    TI__Prodigy 280 points

    Hi Arash,

    I have provided BCLK 1.54MHz and 16Khz (I am able to see 96 ratio for BCLK and FSYNC on GUI) but still same issue i am facing again. Is there anything else i should check?

    Best Regards,

    Rajul

  • 0 in reply to Rajul Bhambay
    TI__Mastermind 30641 points

    Hello,

    Since you are using the GUI, the registers are pretty much set up by themselves, so the only thing that is left is the the inputs to the device. That means 

    (1) the correct clks and (2) the format. 

    For a new set up, I always start at fs=48KHz and I2S format, once I have a working set up, then I change the clks to my need and test it again and then move on to the desired format . This way, if anything causes a problem on each step , I can identify it quickly. 

    I would also plot the LRCLK and BCLK as well DIN on the same screen,  so you can verify the format of input, as well as clks coming to the device are correct. 

    Regards,

    Arash