TAS6584-Q1: How/where to connect regulator bypass pins

Tool/software:

Shall the pins DVDD_RET[2], PLL_RET[64], VREG_RET[15] be connected to the GND-plane on the PCB?

In the datasheet example schematics Figure 9-1 VREG_RET is connect to GND, but DVDD_RET and PLL_RET are not.
In the TIDA-020033 design schematics they are all connected to GND.
TAS6584EVM schematics there Zero-Ohm-resistors.

And shall the pins DVDD_BYP[3] and PLL_BYP[63] be connected on the PCB?

In the datasheet I cannot deduce that from the pin description and the functional block diagram shows an internal connection.
Figure 9-1 shows an additional external connection though. In the TAS6584EVM schematics this external connection exists as well. But in the TIDA-020033 schematics it does not.

I am confused. Does it even matter? All variants seem to work, I guess.

I'd appreciate clarification.

Thanks.

Best Regards

Matthias