TAS3251: Minimum load on the DAC_OUT pins

hi, Sia

Q1,2

i am sorry that this device hasn't consider letting customer put the load at DAC_out pin.

usually, like this kind of pin, we don't recommend customer put the load at these pins for we haven't do any validation for this kind of usecase.

Q3

you can refer this similar plot for reference.

thx

jesse

Hi Jesse,

All my questions above have definite answers, but your response does not answer any of my questions, sorry. 

It would be great if you could have someone with more knowledge about this chip chime in.

Thank you,

Sia

hi Sia

sorry for confusing you.

let me get my reply more clear.

Q1. Testing with our EVM should be the fastest way as we don't have those data in DS. it needs additional testing. if you have evm at hand, you can try to test that.

Q2. this is difficult to test. i am afraid that we don't have this data.

Q3. the plot should be what you want. can you share me what kind of plot and let me see whether i can provide that.

btw, as you said "designing a feedback circuit around TAS3251. The circuit will load the four DAC_OUT (not SPK_OUT) pins of the chip. "

i am not sure whether you have seen any TI document shows reference design. if no, i don't recommend give any load to the DAC_out pin.

as this pin is only be used for tas3251 analog domain input only. if put any load on it, we are not sure whether any chip damage would happen or not.

thanks

jesse

Hi Jesse, 

By "load" I don't mean a 3-phase motor :)  The "load" will have an impedance around 1k. I hope that should not be a problem, but it would be helpful to know the characteristics of the DAC_OUT pins.

Do you know the maximum peak-to-peak swing of the DAC_OUT pins? Would you be able to measure this and let me know?

Currently all the distributors in Canada are sold-out on the EVM. 

Thank you,

Sia

hi Sia

let me check whether myside have the evm for this testing.

i will close this ticket temporarily, the data will be shared to you by email.

thanks

jesse