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TAS2781: PRU emulated I2S Interface

Part Number: TAS2781
Other Parts Discussed in Thread: TLV320AIC3254

Tool/software:

Hi experts, 

Currently we are planning to use the I2S interface that is emulated using the PRUs on I2S.

However, it seems like we cannot provide the I2S signals Fsync & BCLK for TAS2781,

Is there any Audio Converter that can provide these signals to create a point to point connection with AM261 PRUs so that we can the audio amplifier connected to AM261x directly  ? 


Regards,

Alex

  • Hi Alex,

    Can you give more detail on the limitation here? You mean the AM261 doesn't support I2S? What is PRU?

    Thanks,
    Jeff McPherson

  • Hi Jeff,

    The PRU is some IP integrated to AM261x In the subsystem.

    With this IP we are able to emulate I2S with the following setup: 

    to connect to TLV320AIC3254 data sheet, product information and support | TI.com

    However when connecting to

    TAS2781 instead,  I guess we need an input clock from anyhwere. I am not sure how this can be implemented.

    Regards,

    Alex

  • Hi Alex,

    The clocking requirements are different between the TAS2781 and TLV320AIC3254. I am an expert on the codec but the amp is owned by a different team. I will reroute this ticket to them.

    Best regards,
    Jeff McPherson

  • Hi Alex,

    The device clocking is derived from the SBCLK input clock. The tables below show the valid SBCLK clock
    frequencies for each sample rate and SBCLK to FSYNC ratio.
    If the sample rate is properly configured via the SAMP_RATE[2:0] register bits, no additional configuration is
    required as long as the SBCLK to FSYNC ratio is valid. The device will detect improper SBCLK frequencies and
    SBCLK to FSYNC ratios and volume ramp down the playback path to minimize audible artifacts. After the clock
    error is detected, the device will enter a low power halt mode after a time set by CLK_HALT_TIMER[2:0] register
    bits if DIS_CLK_HALT bit is low. Additionally, the device can automatically power up and down on valid clock
    signals if CLK_PWRUD register bit is set to high. The device sampling rate should not be changed while this
    feature is enabled. In this mode the DIS_CLK_HALT bit register should be set low in order for this feature to
    work properly.

  • HI Peter,

    Are there any parts that can provide the I2S clocks themselves ? 

    Is there any HW workaround we can use to connect AM261 to TAS2781 ? 

    Regards,
    Alex

  • Hi Alex,

    When using the AIC3254 connected to the AM261 and it is working. I assume that AIC3254 is in master mode (meaning that the AIC device is generating the BCLK/Frame clock) correct? - is the AM261 PRU not able to act as a clock output?

    TAS2781 cannot act in master mode. it can only operate as an I2S slave. meaning BCLK and FSYNC need to be applied to it. in the table you provided I see that BCLK/FSYNC are identified as INPUT. if these can be OUTPUTs then it should work with TAS2781

    Regards,
    Arthur