PCM5121: abnormal interference on output

Amber Si

Part Number: PCM5121

Tool/software:

Hi team,

My customer use PCM5121 and find output waveform has abnormal interference waveform sometimes, we capture a period of the waveform as attachment. It will lead to THD get worse sometimes.

Can you help comment where interference comes from possibly?

For I2S input , we use AP to test, it is a stable 10kHz /1Vrms sine waveform.

Software configuration as below

Fullscreen dac_config_table.txt Download

#ifndef __MW_PCM5121_CONFIG_TAB_H__
#define __MW_PCM5121_CONFIG_TAB_H__

#include "base_type.h"

const static cfg_reg pcm5121_init_tab[] = {
#if 1
    {0x00, 0x00},// page0
    {0x01, 0x11},// reset
    {0x2B, 0x01},/// set process flowm
    {0x0D, 0x10},// set PLL=BCLK
    {0x25, 0x0C},//ignore SCLK,LRCLK/BCLK halt.
    {0x3D, 0x30},// digital volume 0dB
    {0x3E, 0x30},// digital volume 0dB
    {0x41, 0x00},// disable auto mute
    {0x3F, 0xBB},// ramp up and ramp down setting
    {0x40, 0xB0},// emergency ramp down setting
    {0x28, 0x03},// set data=32bit
    {0x02, 0x00},// normal operate
#else
    {0,  0x00},    /*! page 0 */
    {2,  0x10},    /*! Enter standby mode. */
        {1,  0x11},    /*! Reset modules and registers. */
        {2,  0x00},    /*! Exit standby mode. */
        {13, 0x10},    /*! PLL reference clock select:
                             0: SCK(MCLK)
                             1: BCK.
                        */
        {37, 0x00},    /*! [6]: ignore Fs Detection
                           [5]: ignore BCK Detection
                           [4]: ignore SCK Detection
                           [3]: ignore Clock Halt Detection
                           [2]: ignore LRCK or BCK Missing Detection
                           [1]: disable Clock Divider Autoset
                           [0]: ignore PLL Lock Detection
                        */
        {40, 0x03},    /*! I2S Data Format[5:4]:
                             00: I2S mode.
                             01: DSP.
                             10: RTJ.
                             11: LTJ.
                           I2S Word Length[1:0]:
                             00: 16 bits
                             01: 20 bits
                             10: 24 bits
                             11: 32 bits
                       */
#ifdef AUTO_MUTE_EN
        {65, 0x07},    /*! Auto Mute Control, Enable auto mute */
#else
        {65, 0x00},    /*! Auto Mute Control, Disable auto mute */
#endif
        {0,  0x01},    /*! page 1 */
        {2,  0x11},    /*! Analog Gain Control:
                             Left[4]  0:0dB, 1:-6dB
                             Right[0] 0:0dB, 1:-6dB
                        */
        {5,  0x02},    /*! Disable External Under Voltage Protection, Enable Internal Under Voltage Protection */
        {0,  0x00},    /*! page 0 */
        {43, 0x02},    /*! Low latency IIR interpolation filter with de-emphasis */
        {61, 0x30}, /*! Left  Digital Volume */
        {62, 0x30}, /*! Right Digital Volume */


#endif
};


#endif // __MW_PCM5121_CONFIG_TAB_H__

Amber

over 1 year ago

0 Amber Si over 1 year ago

TI__Intellectual 2445 points

Sorry,

Find upload attachment failed.

Can below file open?

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/6/waveform.7z

0 Arash Loloee over 1 year ago in reply to Amber Si

TI__Mastermind 35191 points

Hi Amber,

Yes, i can open the zip file now. I believe the device is missing a clk edge at those instances,

BCK and FS (LRCLK) should fit in to the following equation and if Fs (for example) is slightly off, after few cycles it can deviate the edge enough that causes a miss of the edge and create a glitch.

BCLK= # of Ch. * Ch depth * Fs

if you plot LRCLK and BCK in the same window , they should be in sync all the time as you move along the time, however right at those glitches you probably can see the edges are shifted ( if the shift accumulates over the time, an edge will be missed.) So my suggestion is to monitor the clks carefully to make sure they are correct and stay in sync.

Also monitor the flags that can detect LRCK or BCK Missing , or clk halt, even though the glitch might no trigger the flags but it is a good idea to monitor those flags (register 0x25). If there is no conflict (PLL in VCOM mode), enable clk divider auto-set .

PLL by default is enabled , so you might want to go thorough the PLL clk coefficients (Table 131/132 whichever is applicable) and make sure they are accurate. Also as an experiment you can change the source for PLL clk or disable the PLL and see if it fixes the problem.

At the any rate, I think the problem is a clk loses its sync every few millisecond.

Let me knw if problem still could not be resolved.

Regards,

Arash

0 Amber Si over 1 year ago in reply to Arash Loloee

TI__Intellectual 2445 points

Hi Arash,

I'll capture the clks waveform to see more information.

And

Arash Loloee said:
lso monitor the flags that can detect LRCK or BCK Missing , or clk halt, even though the glitch might no trigger the flags but it is a good idea to monitor those flags (register 0x25).

I can't find 0x25 register ,but only 0x94 is showing clks flag, do you mean that?

0 Amber Si over 1 year ago in reply to Amber Si

TI__Intellectual 2445 points

and how to enable clk divider auto-set

Arash Loloee said:
enable clk divider auto-set .

0 Arash Loloee over 1 year ago in reply to Amber Si

TI__Mastermind 35191 points

Autoset is in that register as well and is the second LSB bit, DCAS, by default it should be enabled (B0=0)

in your script but the description says you disabled them {0x25, 0x0C},//ignore SCLK,LRCLK/BCLK halt.

Regards,

Arash

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PCM5121: abnormal interference on output