TPA3112D1-Q1: Schematic design issues

Hi Ian

Please check below link.

https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1530168/tpa3112d1-q1-inp

And your description seems different from Ivy.

Could R37 really affect the Fault pin?

I don't know what the reason is, but currently, while other signals are functioning normally in the working mode, after disconnecting R37, the fault pin reported an error (measured as 0V).

After power-on, the fault pins of the product TPA3112D1-Q1 were set low. The captured waveforms and circuit diagrams are as follows

If SD remains in an invalid state after power-on, the fault pin will not be set low.

Could you please help analyze what the reason is

HI Ian

 The INP voltage drops before FAULT pin, is there any thing on your board would affect the input side? What is R38 value on the board, try remove it. And any possible shortage? 

I saw that 7.3.1 in the specification sheet shows that there are two trigger conditions for DC protection.Dc protection can be triggered if either of the following two conditions is met.

1.when the output differential duty-cycle exceeds 14% (for example, 57%, –43%) for more than 420 ms at the same polarity；

2.The minimum differential input voltages required to trigger the DC detect are shown in Table Table 1. The inputs must remain at or above the voltage listed in the table for more than 420 ms to trigger the DC detect.

However, the current set gain is 36dB. During actual measurement, the voltage difference between INP and INN is 17mV and lasts for 420ms, but the DC protection is not triggered. What is the reason for this？

Hi Ian

 Please capture the waveform at Pin11 and Pin12 directly, let's see the waveform first, thanks.

The figure shows the captured power-on waveform. The voltage difference between INP and INN is approximately 1.2V, which lasts for 6 seconds. The SD enable is turned on, and no FAULT is reported.

Hi Ian

Your waveform, INN is always 0V, is not correct. Device need to setup DC bias voltage at all input pins during power up, otherwise would fail to start up.

Could you check all the input cap is fine on your board?

This is the schematic diagram. Please help review it. My INN is grounded here. How can I apply the bias current.

Hi Ian

Where do you captured the waveform? The position 1 or position 2?

The bias voltage would be set up at the capacitor C35, if you test at position 1, should able to find it.

hi 

You asked me to capture the waveforms of Pin11 and PIN 12. PIN11 is INN. I captured a waveform diagram. You said that the voltage of INN has always been 0V, but INN is grounded. How to apply the bias voltage? I saw that the demo board is also grounded. What's wrong with my understanding?