• State TI Thinks Resolved
  • Locked Locked
  • Replies 13 replies
  • Answers 2 answers
  • Subscribers 30 subscribers
  • Views 332 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPA3112D1-Q1: Schematic design issues

ian wu
Intellectual 815 points
Part Number: TPA3112D1-Q1


Tool/software:

hi Expert,

1.Is it okay to design the INP input circuits R37 and R38 in TPA3112D1-Q1 like this? On the left is the voice chip

2.At present, we have found that after disconnecting R37, other signals are supplied normally according to the working mode, but the fault pin reports an error (measured as 0V). Only after re-powering and reconnecting R37 can normal operation be restored. Why is this?

  • 0
    TI__Guru 52090 points

    Hi Ian

    Please check below link.

    https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1530168/tpa3112d1-q1-inp

    And your description seems different from Ivy.

    Could R37 really affect the Fault pin?

  • 0 in reply to Shadow He
    Intellectual 815 points

    I don't know what the reason is, but currently, while other signals are functioning normally in the working mode, after disconnecting R37, the fault pin reported an error (measured as 0V).

  • 0 in reply to ian wu
    TI__Guru 52090 points

    Hi Ian

    Let's check the waveform first. 

    Capture the waveform at both INN and INP, during power up.

    Then compare the condition, with R37 and without R37.

    See any difference for this two condition.

  • 0 in reply to Shadow He
    Intellectual 815 points

    After power-on, the fault pins of the product TPA3112D1-Q1 were set low. The captured waveforms and circuit diagrams are as follows

    If SD remains in an invalid state after power-on, the fault pin will not be set low.

    Could you please help analyze what the reason is

  • 0 in reply to ian wu
    TI__Guru 52090 points

    HI Ian

     The INP voltage drops before FAULT pin, is there any thing on your board would affect the input side? What is R38 value on the board, try remove it. And any possible shortage? 

  • 0 in reply to Shadow He
    Intellectual 815 points

    I saw that 7.3.1 in the specification sheet shows that there are two trigger conditions for DC protection.Dc protection can be triggered if either of the following two conditions is met.

    1.when the output differential duty-cycle exceeds 14% (for example, 57%, –43%) for more than 420 ms at the same polarity；

    2.The minimum differential input voltages required to trigger the DC detect are shown in Table Table 1. The inputs must remain at or above the voltage listed in the table for more than 420 ms to trigger the DC detect.

    However, the current set gain is 36dB. During actual measurement, the voltage difference between INP and INN is 17mV and lasts for 420ms, but the DC protection is not triggered. What is the reason for this？

  • 0 in reply to ian wu
    TI__Guru 52090 points

    Hi Ian

     Please capture the waveform at Pin11 and Pin12 directly, let's see the waveform first, thanks.

  • 0 in reply to Shadow He
    Intellectual 815 points

    The figure shows the captured power-on waveform. The voltage difference between INP and INN is approximately 1.2V, which lasts for 6 seconds. The SD enable is turned on, and no FAULT is reported.

  • 0 in reply to ian wu
    TI__Guru 52090 points

    Hi Ian

    Your waveform, INN is always 0V, is not correct. Device need to setup DC bias voltage at all input pins during power up, otherwise would fail to start up.

    Could you check all the input cap is fine on your board?

  • 0 in reply to Shadow He
    Intellectual 815 points

    This is the schematic diagram. Please help review it. My INN is grounded here. How can I apply the bias current.

  • 0 in reply to ian wu
    TI__Guru 52090 points

    Hi Ian

    Where do you captured the waveform? The position 1 or position 2?

    The bias voltage would be set up at the capacitor C35, if you test at position 1, should able to find it.

  • 0 in reply to Shadow He
    Intellectual 815 points

    hi 

    You asked me to capture the waveforms of Pin11 and PIN 12. PIN11 is INN. I captured a waveform diagram. You said that the voltage of INN has always been 0V, but INN is grounded. How to apply the bias voltage? I saw that the demo board is also grounded. What's wrong with my understanding?

  • 0 in reply to ian wu
    TI__Guru 52090 points

    Hi

    The correct Pin11 and Pin12 waveform should be as below, you could see that after power up, IC will charge this 2 pins together, to around 3V. You could test it on the EVM.

    Your side Pin11 is always 0V, and Pin 12 jump to 3V for a moment and quickly pulled low to 1V, and finally shutdown.

    ian wu said:
    but INN is grounded

    Why INN is grounded. Is C35 on your board or not? As long as C35 is there, the pin 11 is not directly grounded, correct?