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TLV320AIC3106: Device tree configurations when the codec is supplied with an external fixed oscillator

Part Number: TLV320AIC3106
Other Parts Discussed in Thread: AM67A,

Tool/software:

In our application, the TLV320AIC3106 codec has an external 12.288Mhz oscillator connected and then the codec is conncted to mcasp0 interface of an AM67a SoC. Please refer the device tree excerpts below. Since MCLK is not connected to the SoC mcasp interface, the codec is the clock master.

    main_mcasp0_pins_default: main-mcasp0-default-pins {
        pinctrl-single,pins = <
            J722S_IOPAD(0x1a4, PIN_INPUT,  0)  /* (D25) MCASP0_ACLKX  <- BCLK from codec */
            J722S_IOPAD(0x1a8, PIN_INPUT,  0)  /* (C26) MCASP0_AFSX   <- LRCLK from codec */
            J722S_IOPAD(0x1a0, PIN_OUTPUT, 0)  /* (F23) MCASP0_AXR0   -> TX to codec */
            J722S_IOPAD(0x19c, PIN_INPUT,  0)  /* (B25) MCASP0_AXR1   <- RX from codec */
        >;
    };

    clk_audio_osc: clk-audio-osc {
    compatible = "fixed-clock";
    #clock-cells = <0>;
    clock-frequency = <12288000>;
    clock-output-names = "tlv320aic3106-mclk";
    };

    codec_audio: sound {
        compatible = "simple-audio-card";
        simple-audio-card,name = "J722S-EVM";
        simple-audio-card,widgets =
            "Headphone",    "Headphone Jack",
            "Line",        "Line In",
            "Microphone",    "Microphone Jack";
        simple-audio-card,routing =
            "Headphone Jack",    "HPLOUT",
            "Headphone Jack",    "HPROUT",
            "LINE1L",        "Line In",
            "LINE1R",        "Line In",
            "MIC3R",        "Microphone Jack",
            "Microphone Jack",    "Mic Bias";
        simple-audio-card,format = "dsp_b";
        simple-audio-card,bitclock-master = <&sound_master>;
        simple-audio-card,frame-master = <&sound_master>;
        simple-audio-card,bitclock-inversion;

        simple-audio-card,cpu {
            sound-dai = <&mcasp0>;
        };

        sound_master: simple-audio-card,codec {
            sound-dai = <&tlv320aic3106>;
            clocks = <&clk_audio_osc>;
        };
    };

    tlv320aic3106: audio-codec@1b {
        #sound-dai-cells = <0>;
        compatible = "ti,tlv320aic3106";
        reg = <0x1b>;
        ai3x-micbias-vg = <1>;  /* 2.0V */
        AVDD-supply = <&vcodec_3v3>;
        IOVDD-supply = <&vcodec_3v3>;
        DRVDD-supply = <&vcodec_3v3>;
        DVDD-supply = <&vcodec_1v8>;

    }; 

&mcasp0 {
    status = "okay";
    #sound-dai-cells = <0>;
    pinctrl-names = "default";
    pinctrl-0 = <&main_mcasp0_pins_default>;
    op-mode = <0>; /* MCASP_IIS_MODE */
    tdm-slots = <2>;
    serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
           1 0 2 0
           0 0 0 0
           0 0 0 0
           0 0 0 0
    >;
};  

The codec gets detected and the sound card is visible for aplay -l command ,

root@j722s-evm:/home/root# aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: Dummy [Dummy], device 0: Dummy PCM [Dummy PCM]
  Subdevices: 8/8
  Subdevice #0: subdevice #0
  Subdevice #1: subdevice #1
  Subdevice #2: subdevice #2
  Subdevice #3: subdevice #3
  Subdevice #4: subdevice #4
  Subdevice #5: subdevice #5
  Subdevice #6: subdevice #6
  Subdevice #7: subdevice #7
card 1: Loopback [Loopback], device 0: Loopback PCM [Loopback PCM]
  Subdevices: 7/8
  Subdevice #0: subdevice #0
  Subdevice #1: subdevice #1
  Subdevice #2: subdevice #2
  Subdevice #3: subdevice #3
  Subdevice #4: subdevice #4
  Subdevice #5: subdevice #5
  Subdevice #6: subdevice #6
  Subdevice #7: subdevice #7
card 1: Loopback [Loopback], device 1: Loopback PCM [Loopback PCM]
  Subdevices: 8/8
  Subdevice #0: subdevice #0
  Subdevice #1: subdevice #1
  Subdevice #2: subdevice #2
  Subdevice #3: subdevice #3
  Subdevice #4: subdevice #4
  Subdevice #5: subdevice #5
  Subdevice #6: subdevice #6
  Subdevice #7: subdevice #7
card 2: J722SEVM [J722S-EVM], device 0: 2b00000.audio-controller-tlv320aic3x-hifi tlv320aic3x-hifi-0 [2b00000.audio-controller-tlv320aic3x-hifi tlv320aic3x-hifi-0]
  Subdevices: 1/1
  Subdevice #0: subdevice #0

However, when a file is played, an error is thrown.

root@j722s-evm:/home/root# aplay -D plughw:2,0 test.wav   
Playing WAVE 'test.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo
aplay: pcm_write:2178: write error: Input/output error

When debug is enabled, the following is printed to dmesg

[Jun30 09:47]  2b00000.audio-controller-tlv320aic3x-hifi: ASoC: tlv320aic3x-hifi <-> 2b00000.audio-controller info:
[  +0.011289]  2b00000.audio-controller-tlv320aic3x-hifi: ASoC: rate mask 0x7fe
[  +0.007870]  2b00000.audio-controller-tlv320aic3x-hifi: ASoC: ch   min 2 max 2
[  +0.008033]  2b00000.audio-controller-tlv320aic3x-hifi: ASoC: rate min 8000 max 96000
[  +0.010331] tlv320aic3x 3-001b: Update DAI routes for tlv320aic3x-hifi playback
[  +0.008084] davinci-mcasp 2b00000.audio-controller: Update DAI routes for 2b00000.audio-controller playback
[  +0.642632] asoc-simple-card sound: playback write timeout (DMA or IRQ trouble?)
[  +0.671987] asoc-simple-card sound: playback write timeout (DMA or IRQ trouble?)
[  +5.215939]  2b00000.audio-controller-tlv320aic3x-hifi: ASoC: pop wq checking: Playback status: inactive waiting: yes

Please suggest what is missing in our configuration.

  • Hi,

    Apologies for the delay, our linux expert will update this thread shortly

  • Hi Hiran,

    What clocks are you seeing on MCASP0? Like BCLK/WCLK, Can you also provide the register dump of MCASP0?

    The debug log shows rate as 7fe..

    Best Regards,

    Suren

  • Hello Suren,

    Currently this is the setup ->

    MCASP0_ACLKX D25 BCLK
    MCASP0_AFSX C26 WCLK
    MCASP0_AXR1 B25 DIN
    MCASP0_AXR0 F23 DOUT

    MCLK is not routed.

    And the codec MCLK is provided by KC2520Z12.2880C1KX00, an external oscillator which is not connected to the SoC.

    Could you please elaborate on what you mean by register dump? do you want the devmem output of the relevant registers?

    KR,

    Hiran

  • Yes Hiran, devmem2 output of MCASP0 registers should help us understand what might be going wrong.

    What values of BCLK or WCLK are you seeing on D25 and C26 when issuing aplay command? 

    Best Regards,

    Suren

  • Hello Suren, i tried to measure the clocks with an oscilloscope.

    But there weren't any CLK signals available on both lines when the command is run.

    Additionally, devmem2 is failing with the following error -

    root@j722s-evm:/home/root# devmem2 0x02B00000 w
    /dev/mem opened.
    Memory mapped at address 0xffff8fa3f000.
    Bus error (core dumped)

    I tried with setting STRICT_DEVMEM=n and recompiling the kernel, still the result is the same.

    (IO_STRICT_DEVMEM [=n]  ,STRICT_DEVMEM [=n])

    KR,

    Hiran

  • Looks like the codec is not providing the relevant clocks to MCASP and that's why the devmem2 is also failing.

    Can you confirm the clocks on the codec side? 

    Best Regards,

    Suren

  • Hello Suren, which clocks should the codec provide - WCLK and BCLK ? Please excuse my ignorance. I am new to McASP.

    KR,

    Hiran

  • Just checked, no BCLK/WCLK received from the codec. What could be the culprit? no other msgs are printed to dmesg. Are there any other debug logs we can enable?

    KR,

    Hiran

  • Have you verified that the MCLK from external oscillator is correct on the Codec?  If the MCLK is not properly provided  to the coded, the codec would not generate BLCK and WCLK. 

    Best Regards,

    Suren

  • Yeah, the MCLK from the external crystal seems to be fine. 

    Measured at the Codec MCLK pin.

    KR,

    Hiran

  • Can you check why the BCLK and WCLK are not generated from the codec? 

    Best Regards,

    Suren

  • Please find the regdump of the codec below, this was taken after manually unbinding the driver.

    ##############PAGE 0##########################
    
    root@j722s-evm:/home/root# i2cdump -y 3 0x1b b
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 00 00 00 10 04 00 00 00 00 00 00 01 00 00 00 80    ...??......?...?
    10: 80 ff ff 78 78 78 78 78 78 06 00 fe 00 00 fe 00    ?..xxxxxx?.?..?.
    20: 00 00 00 00 00 00 00 00 00 00 00 80 80 00 00 00    ...........??...
    30: 00 00 00 04 00 00 00 00 00 00 04 00 00 00 00 00    ...?......?.....
    40: 00 04 00 00 00 00 00 00 04 00 00 00 00 00 00 00    .?......?.......
    50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    60: 00 00 00 00 00 c0 02 00 00 00 00 00 00 00 00 00    .....??.........
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    80: 00 00 00 10 04 00 00 00 00 00 00 01 00 00 00 80    ...??......?...?
    90: 80 ff ff 78 78 78 78 78 78 06 00 fe 00 00 fe 00    ?..xxxxxx?.?..?.
    a0: 00 00 00 00 00 00 00 00 00 00 00 80 80 00 00 00    ...........??...
    b0: 00 00 00 04 00 00 00 00 00 00 04 00 00 00 00 00    ...?......?.....
    c0: 00 04 00 00 00 00 00 00 04 00 00 00 00 00 00 00    .?......?.......
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 00 00 00 c0 02 00 00 00 00 00 00 00 00 00    .....??.........
    f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    
    ##############PAGE 1##########################
    
    root@j722s-evm:/home/root# i2cset -y 3 0x1b 0x00 0x01
    root@j722s-evm:/home/root# i2cdump -y 3 0x1b b
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 01 6b e3 96 66 67 5d 6b e3 96 66 67 5d 7d 83 84    ?k??fg]k??fg]}??
    10: ee 7d 83 84 ee 39 55 f3 2d 53 7e 6b e3 96 66 67    ?}???9U?-S~k??fg
    20: 5d 6b e3 96 66 67 5d 7d 83 84 ee 7d 83 84 ee 39    ]k??fg]}???}???9
    30: 55 f3 2d 53 7e 7f ff 00 00 00 00 00 00 00 00 00    U?-S~?..........
    40: 00 7f ea 80 16 7f d5 7f ea 80 16 7f d5 00 00 00    .????????????...
    50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    80: 01 6b e3 96 66 67 5d 6b e3 96 66 67 5d 7d 83 84    ?k??fg]k??fg]}??
    90: ee 7d 83 84 ee 39 55 f3 2d 53 7e 6b e3 96 66 67    ?}???9U?-S~k??fg
    a0: 5d 6b e3 96 66 67 5d 7d 83 84 ee 7d 83 84 ee 39    ]k??fg]}???}???9
    b0: 55 f3 2d 53 7e 7f ff 00 00 00 00 00 00 00 00 00    U?-S~?..........
    c0: 00 7f ea 80 16 7f d5 7f ea 80 16 7f d5 00 00 00    .????????????...
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
    

    Is anything misconfigured? This is bound to and configured by tlv320aic3x kernel driver.

    KR,

    Hiran

  • Above might be faulty as the driver was unbound, please find the codec reg dump via regmap (all 110 regs) via /sys/kernel/debug/regmap/3-001b/registers during operation

         00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
    00:  00 XX 00 11 1c 36 b0 8a c0 40 00 01 00 00 00 20
    10:  20 ff ff 00 78 78 00 78 78 00 00 fe 00 00 fe 00
    20:  18 18 00 00 00 00 00 00 40 00 00 a8 a8 2f 2f af
    30:  00 00 00 0c 2f 2f af 00 00 00 0c 00 00 00 2f 2f
    40:  af 0c 00 00 00 2f 2f af 0c 2f 2f af 2f 2f af 08
    50:  2f 2f af 00 00 00 08 00 00 00 2f 2f af 08 00 00
    60:  00 00 00 00 00 00 02 00 00 00 00 00 00 00
    

    KR,

    Hiran

  • Hi Hiran,

    Let me route your query to our audio team for further support as to why you are not seeing BCLK and WCLK generated from the codec.

    Best Regards,

    Suren

  • Hello Suren,

    Appreciate the help.

    KR,

    Hiran

  • Hi Hiran,

    The first issue I see is that the sample rate is 44.1kHz (set with register 7) rather than 48kHz, so if your MCLK is 12.288MHz, there is no integer relation between 44.1k and 12.288MHz. The clock tree in the device requires that the input clock be 256 times the fsref, so if you switch it to 48kHz in register 0x07, then it should resolve the problem and the clocks will be able to generate. If you do need 44.1kHz sample rate, we can configure the PLL and it may be possible to generate as well. Typically 44.1kHz is the default sample rate of a computer, see if you can change your Linux system to be running at 48k, the dts file to default to 48k so the driver changes, or play back a file at 48k etc. Let me know what you are able to change here. 

    Best,
    Mir