PCM6240-Q1: Total Signal Chain latency

Nishka Rao

Intellectual 1466 points

Part Number: PCM6240-Q1

Tool/software:

Hi Team,

I'm trying to calculate the signal chain latency of the PCM6240 and I want to make sure my reasoning is correct.

The Fsync is at 48kHz, and all the modified register settings are shown below.

Adc_RegCfg gPcm6240RegInst0[] =
{
    /* Page select 0 */
    {0x00, 0x00},
    /* Reset */
    {0x01, 0x01},
    /* Page select 0 */
    {0x00, 0x00},
    /* Disable sleep */
    {0x02, 0x09},
    /* High impedance for unused cycles */      //word length 32 bits
    {0x07, 0x31},
    /* 1 BCLK delay between FSYNC and data */
    {0x08, 0x01},
    /* CH1 at slot 0 */
    {0x0B, 0x00},
    /* CH2 at slot 4 */
    {0x0C, 0x04},
    /* CH3 at slot 1 */
    {0x0D, 0x01},
    /* CH4 at slot 5 */
    {0x0E, 0x05},
    /* Set micbias to 5v */
    {0x3b, 0x70},
    /* CH1_CFG0: AC-Coupled , single-ended, LINE input */
    {0x3c, 0xA0},
    /* CH2_CFG0: AC-Coupled , single-ended, LINE input */
    {0x41, 0xA0},
    /* CH3_CFG0: AC-Coupled , single-ended, LINE input */
    {0x46, 0xA0},
    /* CH4_CFG0: AC-Coupled , single-ended, LINE input */
    {0x4b, 0xA0},
    /* Input channel enable */
    {0x74, 0xF0},
    /* Power up micbias and power up all ADC channels */
    {0x75, 0x60},
};

Based on the datasheet, my understanding is the latency from the input signal to when it is seen on the TDM line is given by the below diagram:

By default,

PGA set to 0 DB
Phase Calibration set no delay
Decimation filter: Linear phase Decimation
HPF: cutoff of 0.000025 * fs
Gain Calibration set to 0 DB
Channel summing mode disabled
Biquad Filters:
- Unsure on this
Digital Volume Control set to 0DB

My understanding based on the datasheet and the above parameters, is that the only thing that introduces delay in the system is the Decimation filter.

Table 24 states that the group delay would be 17.1 x (1/fs) = 365.25 us?