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TLV320ADC5120: ADC Sampling Performance

Allan Wegner
Prodigy 30 points
Part Number: TLV320ADC5120

Tool/software:

The data sheet states in Section 3, Description: "......allows for sample rates up to 768 kHz, and allows for sample rates up to 192 kHz."  What is the sample rate of the sigma-delta AGC bock without upsampling?  Is it 768 kHz or 192 kHz, or something else?

  • 0
    TI__Expert 7730 points

    Hi Allan,

    The maximum sampling rate supported by the device is 768kHz. The following application note describes the internal processing blocks that are available for different sampling rates.

    https://www.ti.com/lit/pdf/sbaa494

    The modulator clock is 6.144MHz/5.6448MHz depending on the sampling rate, as described in datasheet.

    Thanks and Regards,

    Lakshmi Narasimhan

  • 0 in reply to Lakshmi Narasimhan Badrinarayanan
    Prodigy 30 points

    No, this response does not resolve our request.  We have read AN sbaa494a, and in particular Section 8.3.6.3.  However, we are not certain of the inherent/basic/fundamental sampling rate of the ADC .  Is the maximum sampling rate of the ADC block 768 kHz achieved without upsampling?

    What is the stability of the external clock required to achieve a LSB jitter of less than 1/2 bit? 

    Regards..........Allan

  • 0 in reply to Allan Wegner
    TI__Expert 7730 points

    Hi Allan,

    Can you clarify what you mean "Is the maximum sampling rate of the ADC block 768 kHz achieved without up sampling"?

    Basically, what the datasheet says is that the delta-sigma modulator clock operates at 6.144MHz (in case of multiples of 48kHz sampling rate), and this is then decimated (down sampled) to get an output data at 768kHz sampling rate.

    Thanks and Regards,

    Lakshmi Narasimhan