Other Parts Discussed in Thread: TAS2574,
Tool/software:
Hi team,
Audio data format: I2S, Left Justified, 32bit length, 64Fs
The following is a description of each channel in the attached image.
CH1: SCLK
CH2: DATA
CH3: LRCK
- From the Timing Requirements, it is assumed that the tLS item specifies the rise time of SCLK from the rise/fall of LRCK.
In the following image, this would be approximately 354.396ns?
- In that case, would SCLK, which is rising at the same timing as LRCK, ever be recognized as the first bit clock depending on the variation in the value of tLS?
- In such a case, should we invert the clock to accommodate this?
In that case, I am concerned that we will not be able to comply with the tSU regulation.
Although the waveform below is a pseudo-inverted SCLK waveform using the oscilloscope function, the measured value is approximately 6.3838 ns compared to the specified value of 8 ns, which does not comply with the regulations.
Is the manufacturer's recommendation to invert the clock and adjust the DATA timing so that tSU can be observed?
Best Regards,
Ryu.
