TAS6424E-Q1: TAS6424E Register 0x28 Bit5 (PHASE_SEL) Configuration and Potential Issues

Hello Gregg-san,

Thank you for your previous response indicating that the PHASE_SEL bit in Register 0x28 affects EMI performance.

To better understand the implications of this setting, I would appreciate your insights on the following points:

1. I understand that the impact is primarily on EMI performance. Could you please confirm whether this includes both radiated and conducted emissions, or if other aspects such as immunity or crosstalk may also be affected?

2. Regarding EMI performance: if PHASE_SEL is mistakenly left at '0' instead of being correctly set to '1', would the EMI performance be expected to degrade compared to the correct setting? Or would it remain the same?

3. If any documentation or measurement data is available showing the difference in EMI performance between PHASE_SEL = 0 and PHASE_SEL = 1, could you kindly share it?

Thank you again for your support and clarification.

Best regards,

N.Tanaka

Tanaka-san,

1. It improves the EMI performance in both radiated and conducted
2. It is expected to be poorer.  In our test system it was poorer if the bit was left at "0".  Your system may be different, that is why we give you the ability to change it.
3. The documentation will be sent via email.

Regards,
Gregg Scott

Dear Gregg-san,

I hope you're doing well.

I just wanted to follow up regarding the documentation you kindly mentioned in your previous message. I haven’t received the email yet, so I wanted to check if it might have been sent to the wrong address or if it's still in preparation.

If needed, I’d be happy to confirm my email address again.

Thank you again for your continued support, and I appreciate your time and assistance.

Best regards,
N. Tanaka

Tanaka-san,

I will look into the email issue.  

Regards,
Gregg Scott

Dear Gregg-san,

Thank you again for sending the documentation directly — I really appreciate your continued support.

As I reviewed the EMI performance data, I wanted to confirm one detail to ensure we interpret the results correctly.

Could you please clarify whether the measurements for the TAS6424-Q1 correspond to the PHASE_SEL = 0 setting, and the measurements for the TAS5424E-Q1 correspond to PHASE_SEL = 1?

I understand from your previous message that PHASE_SEL = 1 improves EMI performance, and I’d like to confirm if this difference is reflected in the comparison between the two devices.

Apologies for the repeated follow-ups, and thank you again for your patience and assistance.

Best regards,
Nobu

Hi Nobu

Tanaka Nobutomo said:

Could you please clarify whether the measurements for the TAS6424-Q1 correspond to the PHASE_SEL = 0 setting, and the measurements for the TAS5424E-Q1 correspond to PHASE_SEL = 1?

You could say that. 

And there's no PHASE_SEL = 1 option in TAS6424-Q1 device.

Dear Shadow-san,

Thank you for your reply and for sharing the documentation directly — I really appreciate your continued support.

As I reviewed the EMI performance data, I wanted to confirm one point to ensure we interpret the results correctly.

From your message, I understand that the TAS6424-Q1 does not have a PHASE_SEL = 1 option, and that the TAS5424E-Q1 may be used as a reference for that configuration. Just to clarify — does the EMI data for TAS6424-Q1 reflect the PHASE_SEL = 0 condition, and the TAS5424E-Q1 data reflect the PHASE_SEL = 1 condition?

If the data does not directly represent the difference between PHASE_SEL = 0 and 1, or if such a comparison is not available, I’d appreciate your guidance. In that case, another internal team may request that EMI measurements be performed internally to evaluate the impact more precisely. Even when I measure, I need a reference to confirm that the EMI measurement result correctly reflects the difference between PHASE_SEL = 0 and 1.

Thank you again for your patience and support.

Best regards,
N. Tanaka

Hi Tanaka-san

Understand your point that needs the data at totally same condition that reflect the truly performance difference. 

But PHASE_SEL is not a selection. Not only TAS6424 doesn't have this choice, TAS6424E datasheet also says that must set to 1 when you use this device. So it means this difference becomes the fundamental difference between this 2 devices. You don't have choice for both of the device. 

There are also other fundamental differences, like the PWM slew rate is different between the devices, we also not allowed customer to change. You can't say that we also make the SR totally same to check the results, that doesn't have realistic purpose. 

Besides, TAS6424E device specially optimized EMC performance, by adding these fundamental changes, they are not exist in TAS6424. If you try your best to remove all these changes in TAS6424E, they just becomes the same IC, what to test then? 

Please kindly let customer know, both of the IC's EMC is tested, under the most suggested and typical using settings, and totally same external set up, could be used to compare EMC results. 

Dear Shadow-san,

Thank you very much for your detailed explanation — I appreciate your time and support.

I understand your point that PHASE_SEL is not a configurable option and that the differences between TAS6424 and TAS6424E are fundamental, including the required PHASE_SEL setting and PWM slew rate.

However, my intention was to confirm whether there is any EMI performance data that directly reflects the impact of the PHASE_SEL bit setting — specifically, a comparison between PHASE_SEL = 0 and PHASE_SEL = 1 under otherwise identical conditions.

Since we are not able to perform EMI measurements on our side, we rely on TI’s data to evaluate the impact of this bit setting. If such comparative data is not available, I would appreciate it if you could confirm that clearly, so we can communicate accordingly within our team.

Thank you again for your continued support and clarification.

Best regards,
Nobutomo Tanaka

Hi Tanaka-san

Tanaka Nobutomo said:

However, my intention was to confirm whether there is any EMI performance data that directly reflects the impact of the PHASE_SEL bit setting — specifically, a comparison between PHASE_SEL = 0 and PHASE_SEL = 1 under otherwise identical conditions.

Sorry, we don't have test data with this settings.

Hi TI team,

Thank you again for your response and for confirming that no test data is available for this specific PHASE_SEL setting.

I understand that PHASE_SEL is not a selectable option and that the device is designed to operate with PHASE_SEL = 1. However, I’d appreciate it if I could ask one final question to help clarify the functional impact of this bit setting.

Would it be possible to explain — even qualitatively — how the device behavior differs when PHASE_SEL is set to "1" versus "0"? For example, something like:  
“When PHASE_SEL = 1, function A behaves as expected (B), but when PHASE_SEL = 0, function A behaves differently (C). As a result, EMI performance becomes poorer.”

We understand that PHASE_SEL must be set to "1" for proper operation, and that this is the recommended and supported configuration. However, due to internal constraints, we missed the timing to update the software, and are now trying to assess the potential impact of the current setting as accurately as possible.

I realize this may be a difficult question to answer definitively, and I truly appreciate your patience and support throughout this discussion.

Best regards,  
N. Tanaka