Tool/software:
Using the PurePath Console 3 to get config register values based on my speaker and project. The output of that is below. The example C code for how to write those registers via I2C is very confusing IMO and I would love some clarification.
Is this following line in the example code correct or should it be a 2 instead of a 1 for the number of bytes?
i2c_write((unsigned char *)&r[i], 1);
For CFG_META_BURST does the number of bytes include the first location byte (so if it says 4 bytes is it really 4 or 5)?
For example, what is the correct writing to I2C for the following section:
{ 0x00, 0x04 },
{ CFG_META_BURST, 4 },
{ 0x60, 0x04 },
{ 0xcc, 0xcc },
{ 0xcd, 0x00 },
A:
i2c_write([0x00, 0x04])
i2c_write([0x60, 0x04, 0xcc, 0xcc, 0xcd])
B:
i2c_write([0x00])
i2c_write([0x60, 0x04, 0xcc, 0xcc])
i2c_write([0xcd, 0x00])
C:
Something else?
===== Full config output from PureConsole unmodified =====
program_0_ROM Mode.h
typedef unsigned char cfg_u8;
typedef union {
struct {
cfg_u8 offset;
cfg_u8 value;
};
struct {
cfg_u8 command;
cfg_u8 param;
};
} cfg_reg;
#define CFG_META_SWITCH (255)
#define CFG_META_DELAY (254)
#define CFG_META_BURST (253)
/* Example C code */
/*
// Externally implemented function that can write n-bytes to the device
// PCM51xx and TAS5766 targets require the high bit (0x80) of the I2C register to be set on multiple writes.
// Refer to the device data sheet for more information.
extern int i2c_write(unsigned char *data, int n);
// Externally implemented function that delays execution by n milliseconds
extern int delay(int n);
// Example implementation. Call like:
// transmit_registers(registers, sizeof(registers)/sizeof(registers[0]));
void transmit_registers(cfg_reg *r, int n)
{
int i = 0;
while (i < n) {
switch (r[i].command) {
case CFG_META_SWITCH:
// Used in legacy applications. Ignored here.
break;
case CFG_META_DELAY:
delay(r[i].param);
break;
case CFG_META_BURST:
i2c_write((unsigned char *)&r[i+1], r[i].param);
i += (r[i].param / 2) + 1;
break;
default:
i2c_write((unsigned char *)&r[i], 1);
break;
}
i++;
}
}
*/
cfg_reg registers[] = {
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0xfd },
{ 0x0d, 0x0d },
{ 0x32, 0x49 },
{ 0x3f, 0x21 },
{ 0x19, 0x80 },
{ 0x0d, 0x0d },
{ 0x5f, 0xc1 },
{ 0x00, 0x00 },
{ 0x0a, 0x03 },
{ 0x1a, 0xfc },
{ 0x1b, 0xa6 },
{ 0x1c, 0xdf },
{ 0x1d, 0xef },
{ 0x30, 0x19 },
{ 0x32, 0x80 },
{ 0x38, 0x00 },
{ 0x30, 0x19 },
{ 0x33, 0x34 },
{ 0x34, 0x4b },
{ 0x35, 0x84 },
{ 0x3c, 0x38 },
{ 0x00, 0x04 },
{ CFG_META_BURST, 4 },
{ 0x60, 0x04 },
{ 0xcc, 0xcc },
{ 0xcd, 0x00 },
{ CFG_META_BURST, 48 },
{ 0x14, 0x1c },
{ 0x94, 0x7a },
{ 0xe1, 0x1f },
{ 0xa3, 0xd7 },
{ 0x0a, 0x22 },
{ 0xb3, 0x33 },
{ 0x33, 0x25 },
{ 0xc2, 0x8f },
{ 0x5c, 0x28 },
{ 0xd1, 0xeb },
{ 0x85, 0x2b },
{ 0xe1, 0x47 },
{ 0xae, 0x2e },
{ 0xf0, 0xa3 },
{ 0xd7, 0x32 },
{ 0x00, 0x00 },
{ 0x00, 0x35 },
{ 0x0f, 0x5c },
{ 0x29, 0x38 },
{ 0x1e, 0xb8 },
{ 0x52, 0x3b },
{ 0x2e, 0x14 },
{ 0x7b, 0x04 },
{ 0xcc, 0xcc },
{ 0xcd, 0x00 },
{ 0x00, 0x03 },
{ CFG_META_BURST, 4 },
{ 0x5c, 0x1e },
{ 0x2e, 0x14 },
{ 0x7b, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x60, 0x21 },
{ 0x3d, 0x70 },
{ 0xa4, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x64, 0x24 },
{ 0x4c, 0xcc },
{ 0xcd, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x68, 0x27 },
{ 0x5c, 0x28 },
{ 0xf6, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x6c, 0x2a },
{ 0x6b, 0x85 },
{ 0x1f, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x70, 0x2d },
{ 0x7a, 0xe1 },
{ 0x48, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x74, 0x30 },
{ 0x8a, 0x3d },
{ 0x71, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x78, 0x33 },
{ 0x99, 0x99 },
{ 0x9a, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x7c, 0x36 },
{ 0xa8, 0xf5 },
{ 0xc3, 0x00 },
{ 0x00, 0x04 },
{ CFG_META_BURST, 4 },
{ 0x08, 0x39 },
{ 0xb8, 0x51 },
{ 0xec, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x0c, 0x3c },
{ 0xc7, 0xae },
{ 0x14, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x10, 0x3f },
{ 0xd7, 0x0a },
{ 0x3d, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x54, 0x17 },
{ 0x99, 0x99 },
{ 0x9a, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x6c, 0x00 },
{ 0x00, 0x00 },
{ 0x19, 0x00 },
{ 0x00, 0x00 },
{ 0x03, 0x20 },
{ 0x04, 0xf6 },
{ 0x0a, 0x03 },
{ 0x12, 0x12 },
{ 0x13, 0x76 },
{ 0x14, 0x01 },
{ 0x15, 0x2e },
{ 0x17, 0x0e },
{ 0x19, 0x00 },
{ 0x33, 0x34 },
{ 0x34, 0x4b },
{ 0x3b, 0x38 },
{ 0x3d, 0x08 },
{ 0x3e, 0x10 },
{ 0x3f, 0x00 },
{ 0x40, 0xb6 },
{ 0x00, 0x01 },
{ 0x08, 0x40 },
{ 0x00, 0x02 },
{ CFG_META_BURST, 4 },
{ 0x0c, 0x40 },
{ 0x00, 0x00 },
{ 0x00, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x10, 0x03 },
{ 0x4a, 0x51 },
{ 0x6c, 0x00 },
{ 0x00, 0x04 },
{ CFG_META_BURST, 12 },
{ 0x74, 0x7f },
{ 0xfb, 0xb6 },
{ 0x14, 0x80 },
{ 0x04, 0x49 },
{ 0xed, 0x7f },
{ 0xf7, 0x6c },
{ 0x28, 0x00 },
{ 0x00, 0x02 },
{ CFG_META_BURST, 12 },
{ 0x68, 0x7f },
{ 0xfb, 0xb6 },
{ 0x14, 0x80 },
{ 0x04, 0x49 },
{ 0xed, 0x7f },
{ 0xf7, 0x6c },
{ 0x28, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x14, 0x2d },
{ 0x6a, 0x86 },
{ 0x6f, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x18, 0x47 },
{ 0x5c, 0x28 },
{ 0xf6, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x1c, 0x16 },
{ 0x66, 0x66 },
{ 0x66, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x20, 0x1a },
{ 0x66, 0x66 },
{ 0x66, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x24, 0x08 },
{ 0x00, 0x00 },
{ 0x00, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x28, 0x17 },
{ 0x33, 0x33 },
{ 0x33, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x2c, 0x15 },
{ 0x99, 0x99 },
{ 0x9a, 0x00 },
{ 0x00, 0x05 },
{ CFG_META_BURST, 4 },
{ 0x24, 0x7f },
{ 0xfe, 0xfd },
{ 0x47, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x2c, 0xfe },
{ 0xfe, 0xa4 },
{ 0xb5, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x40, 0x00 },
{ 0x00, 0x03 },
{ 0x20, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x44, 0x02 },
{ 0x46, 0xb4 },
{ 0xe4, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x1c, 0x01 },
{ 0xc9, 0x24 },
{ 0x92, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x20, 0x00 },
{ 0x12, 0x49 },
{ 0x25, 0x00 },
{ 0x00, 0x02 },
{ CFG_META_BURST, 4 },
{ 0x5c, 0x00 },
{ 0x01, 0x09 },
{ 0x45, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x64, 0x00 },
{ 0x00, 0x12 },
{ 0xc0, 0x00 },
{ 0x00, 0x04 },
{ CFG_META_BURST, 4 },
{ 0x64, 0x00 },
{ 0x00, 0x00 },
{ 0x00, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x40, 0x04 },
{ 0xcc, 0xcc },
{ 0xcd, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x4c, 0x00 },
{ 0x00, 0x00 },
{ 0x00, 0x00 },
{ 0x00, 0x03 },
{ CFG_META_BURST, 4 },
{ 0x24, 0x39 },
{ 0x80, 0x00 },
{ 0x00, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x18, 0x72 },
{ 0x14, 0x82 },
{ 0xc0, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x1c, 0x00 },
{ 0x00, 0x00 },
{ 0x64, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x20, 0x40 },
{ 0xbd, 0xb7 },
{ 0xc0, 0x00 },
{ CFG_META_BURST, 4 },
{ 0x28, 0x2d },
{ 0x6a, 0x86 },
{ 0x6f, 0x00 },
{ 0x00, 0x00 },
{ 0x04, 0xf6 },
{ 0x0a, 0x03 },
{ 0x31, 0x40 },
};
