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TLV320AIC3254: Query on Noise Cancellation and miniDSP usage in TLV320AIC3254

vandana gunji
Prodigy 10 points
Part Number: TLV320AIC3254

Tool/software:

I am working with the TLV320AIC3254 codec in my project. I have two analog microphones and two digital microphones connected to the codec. I want to be able to use either the analog or digital microphones for signal processing.

My requirement is to perform different noise cancellation techniques, such as:

  1. Active Noise Cancellation (ANC)

  2. Acoustic Echo Cancellation (AEC)

  3. Beamforming

  4. Adaptive Filters

    I have a few questions regarding the codec:

    1. What is the purpose of the processing block and the miniDSP in the TLV320AIC3254? Are these two designed to do the same work, or do they serve different purposes? If different, could you explain what type of operations can be implemented in the processing block versus the miniDSP?

    2. What is the recommended way to use the miniDSP versus the processing blocks in the TLV320AIC3254 in the Pure Path Studio? In which cases should I rely on the built-in processing blocks, and in which cases should I program the miniDSP using PurePath Studio?

    3. From the TI support forums, I found the note:

      • “It cannot keep up with modern expectations of AEC and ANC. We strongly discourage designers from using the DSP in the codec to host the algorithm and instead host the algorithm on a separate DSP or SoC.”
        Based on this, I would like to confirm: Is it correct that advanced algorithms like ANC and AEC cannot be fully supported in the codec’s miniDSP, and are better implemented on an external DSP/SoC?

    4. I also found a note saying:

      • “Adaptive filtering function will not be able to provide noise cancellation. Noise cancellation requires inverting the noise and using it to cancel the noise, rather than just using biquad filtering to filter it out.”
        Could you please clarify this statement in the context of the miniDSP? Does it mean the adaptive filter blocks in the codec are not sufficient for real ANC implementations.

    5. could you please suggest which noise cancellation techniques are practically possible to implement on the TLV320AIC3254 codec itself?
  • 0
    TI__Genius 12615 points

    Hi,

    I will go through your questions one by one.

    A: The processing blocks are the built-in processing systems available on the device WITHOUT using miniDSP. If you want to use miniDSP, the processing block no longer is used, and vice versa. The main thing the processing blocks are used for is changing the signal chain of how many filters are used as well as if the AGC is able to be enabled. There are some user-programmable biquad filters as well as FIR and IIR filters. You would use a processing block when you are not using miniDSP, and in fact will always be one enabled if miniDSP is not used. MiniDSP is what you would use PurePath Studio to configure. There are of course filters and AGC, but also complex routing is able to be done, and specific algorithms can be run. There are too many options to list, I would recommend you download PurePath Studio (PPS) and see if there are options that you would like to use. Here are some screenshots of the options for the miniDSP algos:

    B: Processing blocks would be if you are not using miniDSP. If you just want some filters, don't use miniDSP. If you want any of the routing or algorithms to use, you can use miniDSP.

    C: Noise cancellation would require another DSP. The miniDSP on the AIC3254 does have a "noise reduction" algorithm, but this will be a rudimentary one made out of filters. Noise cancellation involves playing back an inverted signal and processing, I believe this is too much too fast for the DSP to handle in this device. Most of the interesting algorithms that exist for this device only work at 16kHz sample rate or below, so this also would be too low for an appropriate response in a real AEC/ANC system. There used to be an AEC algorithm in PPS for this device but it has since been removed, I believe it did not work well.

    D: Adaptive filtering is able to be enabled in both miniDSP and processing blocks, I believe. In this device, adaptive filtering is when the filter coefficients can be changed while the device is on and already passing data through. There is a double buffer for the filter coefficients, so when one filter is being used, you can change the coefficients in the other buffer and then switch it over. The idea in a noise cancellation system would be to adapt the filters to cancel out background noise, and adjust it based on a microphone input. However, again this is just filters, and there is some latency for the coefficient buffers switching - and this is not technically noise cancellation, just a noise reduction via filtering. Often background noise is also in the voice band or audio band that you would want to hear, so filtering would also harm the quality of the sound intended. Real noise cancellation inverts the noise so that the signal that is desired can be unaffected.

    E: Mainly filtering-oriented algorithms are most optimal to run on the codec itself, and gain level adjustments. Any of the effects I showed in the screenshots are reasonable to use. I also think miniDSP is useful to route signals through various inputs and outputs through mixers and splitters and such.

    Best,
    Mir

  • +1 in reply to Mir Jeffres
    Prodigy 10 points

    Hi,
    Mir

    Thank you for the clear explanation and for clarifying my doubts regarding the noise cancellation techniques of TLVAIC3254 CODEC
    i have another query regarding  Digital Mic Connection and Record/Playback Paths in TLV320AIC3254.

    1.Digital Mic and ADC Connection

          In the reference guide, it shows that digital microphones are attached to the ADC. Since I am using an I²S digital microphone, which already outputs         a digital bitstream, I am confused about the purpose of this connection.

          If the mic already provides digital data, what additional role does the ADC stage have in this case.

    2.Record and Playback Paths
    I would like clarification on the execution of the record and playback paths inside the TLV320AIC3254.

               In which part of the record path are the digital microphones connected

               In which part of the playback path is the digital mic data routed?



  • +1 in reply to vandana gunji
    TI__Genius 12615 points

    Hi,

    Typically when we are talking about digital microphones we are talking about PCM digital microphones, not I2S mics. PCM microphones output data that is about the same as the ADC encoded data internal to the device, NOT I2S - it uses the modulator clock as its clock for the digital data. If your microphone outputs I2S, it does not need to go through the ADC at all, instead you would use it as the input to the DAC. 

    Best,
    Mir

  • 0 in reply to Mir Jeffres
    Prodigy 10 points

    Hi ,
    Mir 
    Thankyou for the Response.
    I have another query regarding digital microphones. I am using two I²S MEMS microphones (primary – left channel and secondary – right channel). In the TLV320AIC3254 codec, where are these digital microphones connected?




  • 0 in reply to vandana gunji
    Prodigy 10 points

    Hi,
    Mir

    I have another query regarding the Adaptive Filters. When we enable the adaptive filters through the registers, we load the coefficients into Buffer A, and initially, we also copy the same coefficients into Buffer B.( this is is my assumption, copying the same coefficients of Buffer A in  Buffer B, correct me if i am wrong)

    My question is: while Buffer A is executing in the codec, if we want to modify the coefficients in Buffer B, do we need to manually update the filter coefficients by writing them through registers, or will the codec automatically adjust the coefficients according to the signal characteristics for smooth adaptation?




  • 0 in reply to vandana gunji
    TI__Mastermind 46355 points

    Hi Vandana,

    The device will not update Buffer A or Buffer B on its own. The host must provide the new coefficients to be loaded into the buffer.

    Best regards,
    Jeff McPherson

  • 0 in reply to vandana gunji
    Prodigy 10 points

    Is my understanding correct that the Digital I²S MEMS microphones connect directly to the miniDSP D ?

  • +1 in reply to vandana gunji
    TI__Genius 12615 points

    Hi,

    Yes, if your microphone outputs I2S, then you can connect to the DIN pin and I2S clock pins. DIN pin should be the input to miniDSP D - you will need to use an "I2S IN" block in PPS if you were using PPS.

    Best,
    Mir

  • 0 in reply to Mir Jeffres
    Prodigy 10 points

    Thankyou Mir,
    I have a query regarding the clock generation in the TLV320AIC3254 codec.
    I am using the PLL to generate my desired sampling rate, I am not able to be generating the sampling rate(WCLK) and Bit clock.  I have followed the process shown in the attached clock-tree diagram

    Her my MCLK is 12MHZ, and MCLK is the input to PLL_CLKIN.




    i am taking the ADC_MOD_CLK input to BDIV_CLKIN



    i want to generate the sampling rate of 48khz 
    i have configured all register values regarding PLL from reference guide.
    Register - 4      value -0x43
    Register - 5      value -0x91
    Register - 6      value -0x07
    Register - 7      value -0x06
    Register - 8      value -0x90
    Register - 11      value -0x82
    Register - 12     value -0x87
    Register - 13      value -0x00
    Register - 14     value -0x80
    Register - 18      value -0x87
    Register - 19     value -0x82
    Register - 20      value -0x80
    Register - 27      value -0x3c
    Register - 28      value -0x00
    Register - 29     value -0x03
    Register - 30      value -0x88




  • 0 in reply to vandana gunji
    TI__Genius 12615 points

    Hi,

    There are a few things you should change here to get the right clocks out. First, register 4 should be set to 0x03, this "high PLL range" is seen in this table from the reference guide:

    With these PLL settings of J.D = 7.1680 or 7.560, the PLL_CLK will be too low for the "high PLL clock range" starting at 92MHz. 

    Next, I would recommend that NDAC=NADC and MDAC=MADC, I see in this example it sets NADC=7 and NDAC=2, and then vice versa for MADC/MDAC. It may be better if you set these to be the same, just in case for future reference if you are using a different clock as an output and get confused why the DAC internal clocks are different than the ADC clocks. It will not affect your specific problem right now since you are using ADC_MOD_CLK as the BCLK divider input, which is after both N and M dividers.

    Finally, if I do the calculation to get what your ADC_MOD_CLK will be -> 12MHz * 7.1680/(7*2) = 6.144MHz. You used BCLK NDIV of 8, so that would be this divided by 8, but since you selected I2S 32 bit, we expect the BCLK to be 48kHz * 32 * 2 = 3.072MHz. So, your BCLK NDIV should be 2 instead (register 30 to 0x82).

    Let me know if this fixes the problem or if you are still having issues.

    Best,
    Mir