PROCESSOR-SDK-AM67: BeagleY AI uname 6.1.83 + ADCx140EVM-PDK . 4 TDM, 48000 hz, 16kbit. codec slave, codec master

Valerii Repin

Part Number: PROCESSOR-SDK-AM67
Other Parts Discussed in Thread: TLV320ADC5140

Tool/software:

Hi Guys here again.

We give up get 4 channels from RP5+TVL320ADC5140 and decided to swich towards BeagleY_AI + TVL320ADC5140. After one day of struggle to connect to part together I am return back.

1) From official tool was taken lates Debian 13 V6.1x-ti XFCE. After OS initialization it do not have any related stuff for SND_SOC_TLV320ADCX140 family , C/h drivers, dtbo files. By fakeroot make -j$(nproc) bindeb-pkg was taken linux image, recompile all modules , now uname -r give 6.1.83,

2) SND_SOC_TLV320ADCX140 now ok, c/h drivers ok, on i2c situation below:

root@beagleboard:/home/bb# i2cdetect -l
i2c-1 i2c OMAP I2C adapter I2C adapter
i2c-2 i2c OMAP I2C adapter I2C adapter
i2c-3 i2c OMAP I2C adapter I2C adapter
i2c-4 i2c OMAP I2C adapter I2C adapter
i2c-5 i2c OMAP I2C adapter I2C adapter

root@beagleboard:/home/bb# i2cdetect -y 1
Warning: Can't use SMBus Quick Write command, will skip some addresses
0 1 2 3 4 5 6 7 8 9 a b c d e f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: -- -- -- -- 54 -- -- -- -- -- -- -- -- -- -- --
60:
70:
root@beagleboard:/home/bb#

root@beagleboard:/home/bb# i2cdetect -y 2
Warning: Can't use SMBus Quick Write command, will skip some addresses
0 1 2 3 4 5 6 7 8 9 a b c d e f
00:
10:
20:
30: UU -- -- -- -- -- -- --
40:
50: UU -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60:
70:
root@beagleboard:/home/bb#

Could you help whit rest of adjustment for slave and master mode for alsa, dts/dtbo files, for extlinux.conf as well, for registry settings for TVL320ADC5140 to get 4 channels from ADC

Thank you for help.

1 month ago

0 Valerii Repin 1 month ago

Prodigy 20 points

update here. TVL320 took 0x4c but driver do not loaded

root@beagleboard:/home/bb# i2cdetect -y -r 1
0 1 2 3 4 5 6 7 8 9 a b c d e f
00: -- -- -- -- -- -- -- --
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
40: 40 -- -- -- -- -- -- -- -- -- -- -- 4c -- -- --
50: -- -- -- -- 54 -- -- -- -- -- -- -- -- -- -- --
60: -- -- -- -- -- 65 -- -- -- -- -- -- -- -- -- --
70: -- -- -- -- -- -- -- --
r

root@beagleboard:/home/bb# i2cdump -y 1 0x4c
No size specified (using byte-data access)
0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
00: 00 00 00 00 00 05 00 30 00 00 00 00 01 02 03 04 .....?.0....????
10: 05 06 07 02 48 ff 10 10 04 20 02 08 00 00 02 40 ????H.??? ??..?@
20: 00 22 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ."..............
30: 00 00 00 ff 00 00 00 00 00 00 00 00 00 00 c9 80 ..............??
40: 00 00 00 c9 80 00 00 00 c9 80 00 00 00 c9 80 00 ...??...??...??.
50: 00 00 c9 80 00 00 00 c9 80 00 00 00 c9 80 00 00 ..??...??...??..
60: 00 c9 80 00 00 00 00 00 00 00 00 01 40 7b 00 00 .??........?@{..
70: e7 00 00 f0 00 00 00 80 00 00 ff 00 ff 8c 00 00 ?..?...?.....?..
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

0 Suren Porwar 1 month ago in reply to Valerii Repin

TI__Mastermind 30175 points

Hi Valerii,

Please refer the below document on understanding the MCASP operation and direction of PINs(Input/Output) and Master/Slave configuration.

https://www.ti.com/lit/pdf/sprack0

Also for reference, you can look at our device tree where our codec is the master(clock initiator).

https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-j722s-evm.dts?h=ti-linux-6.12.y#n206

Audio related documentation can be found in the link below:

https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-am67/11_00_10_01/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Audio.html

Hope this helps

Best Regards,

Suren

0 Valerii Repin 1 month ago in reply to Suren Porwar

Prodigy 20 points

Hi Man. Thank for standard answer. It is do not help so much. Could you tell me why alsa do no upload driver for tlv320adc5140?

I already bought 2 TI products, spend my money and could not connect them together!

Here is dump of 3 commands after all settings initialization, 3 of them give nothing:

root@beagleboard:/home# sudo depmod -a
| grep tlv320sudo modprobe snd-soc-tlv320adcx140
lsmod | grep tlv320
root@beagleboard:/home#

Let check step by step what was done, and where we got bug.

1) snd-soc-tlv320adcx140.ko - created and loaded to system

2) dts/dtbo created and placed in /overlay

3) extlinux.conf changed

Linux won’t load the tlv320adcx140 driver at boot, alsa do not see card.

0 Suren Porwar 1 month ago in reply to Valerii Repin

TI__Mastermind 30175 points

Hi Valerii,

I assume you have referred the below FAQ in porting the driver.

[FAQ] TLV320ADC5140: Is there a Linux Driver for the TLV320ADC5140 family of devices?

Since its more of the ADC issue, I am routing the query to our Audio team, for further support.

Best Regards,

Suren

0 Valerii Repin 1 month ago in reply to Suren Porwar

Prodigy 20 points

please do, as you could not help. This is not ADC issue it look like Linux issue.

Best regards

Valeriy

0 Suren Porwar 1 month ago in reply to Valerii Repin

TI__Mastermind 30175 points

While the team responds, can you share the DTS changes you made in order to add the ADC as soundcard.

Does adding dummy sound card work?

For using Dummy codec in DTS, you will need to apply the following patch

https://patchwork.kernel.org/project/alsa-devel/patch/5652E348.8080002@invoxia.com/

Device tree changes to include dummy codec and register as dummy sound card.

Example DTS to include the dummy codec.

codec_test: codec_test {
compatible = "linux,snd-soc-dummy";
#sound-dai-cells = <0>;
status="okay";
};

codec_test: codec_test {
                compatible = "linux,snd-soc-dummy";
                #sound-dai-cells = <0>;
                status="okay";
        };



codec_audio: sound {

                compatible = "simple-audio-card";
                simple-audio-card,name = "AM62X-DUMMY";
                simple-audio-card,format = "i2s";
                simple-audio-card,bitclock-master = <&sound_master0>;
                simple-audio-card,frame-master = <&sound_master0>;



                sound_master0: simple-audio-card,cpu {
                sound-dai = <&mcasp1>;
                system-clock-direction-out;
                };



                simple-audio-card,codec {
                        sound-dai = <&codec_test>;
                };
        };

Best Regards,

Suren

0 Valerii Repin 1 month ago in reply to Suren Porwar

Prodigy 20 points

here is lates Suren

/dts-v1/;
/plugin/;

/*
 * BeagleY-AI (AM67A) + TLV320ADC5140
 * Mode: Codec-Slave (SoC is clock master)
 * Bus: McASP1 on 40-pin HAT header (PCM_* signals)
 * Format: DSP_A (TDM), 4 slots x 16-bit, fs = 16 kHz (BCLK = 1.024 MHz)
 *
 * Wiring on 40-pin HAT:
 *   Pin 12  -> PCM_CLK   = mcasp1_aclkx  (BCLK, SoC -> codec)
 *   Pin 35  -> PCM_FS    = mcasp1_afsx   (FSYNC, SoC -> codec)
 *   Pin 38  -> PCM_DIN   = mcasp1_axr0   (DATA IN to SoC  <- codec DOUT)
 *   Pin 40  -> PCM_DOUT  = mcasp1_axr1   (DATA OUT from SoC; not used here)
 *   Pin 3/5 -> I2C1 SDA/SCL (codec control, default addr 0x48)
 *   GND     -> GND
 *
 * Notes:
 *   - MCLK (AHCLKX) is not present on the HAT header; the codec can lock from BCLK/FSYNC via PLL.
 *   - mcasp0 is used by HDMI on your system; this overlay uses mcasp1 to avoid conflicts.
 */

&{/} {
        compatible = "ti,am67a-beagley-ai";

        /* -------------------------------------------------------------
         * Enable & configure McASP1 as capture on AXR0 in TDM4.
         * We DO NOT attach a pinctrl here because your base DT already
         * applied "main-mcasp1-default-pins".
         * ------------------------------------------------------------- */
        fragment@1 {
                target = <&mcasp1>;
                __overlay__ {
                        status = "okay";

                        /* 0 = MCASP_IIS_MODE (I2S/TDM framing) */
                        op-mode = <0>;

                        /* Single data-in serializer using AXR0 in TDM4 */
                        tdm-slots = <4>;
                        serializers = <1>;

                        /* Direction bitmask for active serializers:
                         * 1 = IN  (AXR0 is input to the SoC, receiving codec DOUT)
                         */
                        serial-dir = <1>;
                };
        };

        /* -------------------------------------------------------------
         * TLV320ADC5140 on I2C1 (pins 3/5 on the HAT header)
         * Verify the bus label ("&i2c1") matches your running DT.
         * ------------------------------------------------------------- */
        fragment@2 {
                target = <&i2c1>;
                __overlay__ {
                        #address-cells = <1>;
                        #size-cells = <0>;

                        tlv5140: tlv320adcx140@4c {
                                compatible = "ti,tlv320adcx140","ti,tlv320adc5140"; /* covers 5140 */
                                reg = <0x4c>;                    /* confirm with i2cdetect -y 1 */
                                #sound-dai-cells = <0>;

                                /* If RESET is wired, add it here:
                                 * reset-gpios = <&main_gpio? N GPIO_ACTIVE_LOW>;
                                 */
                        };
                };
        };

        /* -------------------------------------------------------------
         * simple-audio-card glue: SoC (McASP1) is bitclock/frame master.
         * TDM4 @ 16-bit. fs=16 kHz -> BCLK = 16k * 4 * 16 = 1.024 MHz.
         * ------------------------------------------------------------- */
        fragment@3 {
                target-path = "/";
                __overlay__ {
                        sound_tlv5140 {
                                compatible = "simple-audio-card";
                                simple-audio-card,name   = "TLV320ADC5140-4ch-16k-CodecSlave";
                                simple-audio-card,format = "dsp_a";

                                /* SoC provides BCLK/FSYNC; codec is slave */
                                simple-audio-card,bitclock-master = <&cpu_dai>;
                                simple-audio-card,frame-master    = <&cpu_dai>;

                                /* If you externally feed MCLK=12.288MHz to codec, you may hint:
                                 * simple-audio-card,mclk-fs = <256>;
                                 */

                                cpu_dai: simple-audio-card,cpu {
                                        sound-dai = <&mcasp1>;

                                        /* Must match codec serial-port config */
                                        dai-tdm-slot-num   = <4>;
                                        dai-tdm-slot-width = <16>;

                                        /* Optionally restrict slots (0..3):
                                         * dai-tdm-slot-mask = <0x0F>;
                                         */
                                };

                                codec_dai: simple-audio-card,codec {
                                        sound-dai = <&tlv5140>;
                                };
                        };
                };
        };
};

0 Valerii Repin 1 month ago in reply to Suren Porwar

Prodigy 20 points

Suren look on date, 10 years ago) Nov. 23, 2015, 9:58 a.m. UTC

0 Suren Porwar 1 month ago in reply to Valerii Repin

TI__Mastermind 30175 points

Yes the patch still holds good to test simple-card without any codec connected.

We also have a similar patch if you want to try that instead:

https://github.com/jailuthra/linux/commit/2d577a938d24f238edb19c8481dbb7136ff43cf6

Also, For Beagle boards, could you try asking on the Beagle community on their forum page? Beagle uses a modified version of the SDK from TI to run their debian-based images.

Best Regards,

Suren

0 Niranjan Holalu Yogendra 1 month ago in reply to Valerii Repin

TI__Prodigy 170 points

Valerii Repin

Looks to me like the i2c probe is not happening due to some issue with the device tree or i2c.

I am assuming that modules are loaded. But the probe has not happened.

----

Is the I2c probe successful ? Since in your DTS file, there is no reset gpio, we can expect that the following info message to be seen

https://elixir.bootlin.com/linux/v6.1.83/source/sound/soc/codecs/tlv320adcx140.c#L1162

Also, I think you can try adding the following lines

1. for i2c.

status = "okay";

                target = <&i2c1>;
                __overlay__ {
                        status = "okay";
                        #address-cells = <1>;
                        #size-cells = <0>;

2. compatible, I think we can try with only one device.

compatible = "ti,tlv320adc5140"; /* covers 5140 */

Hope this makes sense.

- Niranjan

0 Valerii Repin 1 month ago in reply to Niranjan Holalu Yogendra

Prodigy 20 points

Hi Niranjan.

i added yesterday, situation was get worse. I will try again.

could it be conflict od tlv codec abd hdmi? They both claim 0x4c address. I swich of hdmi in dts. It is switched off. hdmi card gone in alsa but on i2c-4 we have UU on 0x4c. It look like custom dtbo working partly.

Valerii

0 Valerii Repin 1 month ago in reply to Niranjan Holalu Yogendra

Prodigy 20 points

hdmi was problem.

beagle@beagle:~$ arecord -l
**** List of CAPTURE Hardware Devices ****
card 0: TLV320ADC51404c [TLV320ADC5140-4ch-16k-CodecSlav], device 0: davinci-mcasp.0-tlv320adcx140-codec tlv320adcx140-codec-0 [davinci-mcasp.0-tlv320adcx140-codec tlv320adcx140-codec-0]
Subdevices: 1/1
Subdevice #0: subdevice #0

0 Valerii Repin 1 month ago in reply to Valerii Repin

Prodigy 20 points

beagle@beagle:~$ arecord -D hw:0,0 --dump-hw-params
Warning: Some sources (like microphones) may produce inaudible results
with 8-bit sampling. Use '-f' argument to increase resolution
e.g. '-f S16_LE'.
HW Params of device "hw:0,0":
--------------------
ACCESS: MMAP_INTERLEAVED RW_INTERLEAVED
FORMAT: S16_LE
SUBFORMAT: STD
SAMPLE_BITS: 16
FRAME_BITS: [16 64]
CHANNELS: [1 4]
RATE: [16000 192000]
PERIOD_TIME: (166 2048000]
PERIOD_SIZE: [32 32768]
PERIOD_BYTES: [64 65536]
PERIODS: [2 8192]
BUFFER_TIME: (333 16384000]
BUFFER_SIZE: [64 262144]
BUFFER_BYTES: [128 524288]
TICK_TIME: ALL

[ 205.455592] davinci-mcasp 2b10000.audio-controller: Too fast reference clock (96000000)

0 Valerii Repin 1 month ago in reply to Niranjan Holalu Yogendra

Prodigy 20 points

Hi Niranjan.

could you give hint how to get BCLK and FSYN from McASP? now there is nothing after starting record. on RP as soon as press enter there was 48 000 khz and 1,2 mhz impulses.

0 Niranjan Holalu Yogendra 1 month ago in reply to Valerii Repin

TI__Prodigy 170 points

Suren Porwar is the right person for the McASP related configuration. Please comment.

But couple of things I note is, in your previous dts snippet, it is being done with setting *,cpu node as master using "frame-master" and "bitclock-master" properties ( simple-card.txt ). Also in Suren's example, looks to me like mcasp is configured as master.

    simple-audio-card,format = "i2s";
    simple-audio-card,bitclock-master = <&sound_master0>;
    simple-audio-card,frame-master = <&sound_master0>;

    sound_master0: simple-audio-card,cpu {
        sound-dai = <&mcasp1>;
        system-clock-direction-out;
    };

If it still did not work, need to check with Suren.

0 Suren Porwar 1 month ago in reply to Niranjan Holalu Yogendra

TI__Mastermind 30175 points

Hi Valerii,

If MCASP is configured to be Master, Can you share the output of k3conf dump clocks | grep MCASP1 to understand if AUXCLK is being sent to AHCLKR/AHCLKX to generate the BCLK and LRCLK using the dividers.

Can you share what is the expected BCLK and LRCLK are? Are you able to see any of these the MCASP pins?

On our EVM, we use MCASP as slave, but as I shared the snippet before, the MCASP can be configured as Master which would take AUXCLK as the input to generate the MCASP clocks.

Best Regards,

Suren

0 Valerii Repin 1 month ago in reply to Suren Porwar

Prodigy 20 points

Hi Suren.

DEV_MCASP1_AUX_CLK is READY and currently showing 96 MHz.

system-controller@44043000 {
compatible = "ti,k2g-sci";
ti,host-id = <0x0c>;
mbox-names = "rx", "tx";
mboxes = <0x1d 0x0c 0x1d 0x0d>;
reg-names = "debug_messages";
reg = <0x00 0x44043000 0x00 0xfe0>;
bootph-all;
ti,partial-io-wakeup-sources = <0x1e 0x1f 0x20 0x21>;
phandle = <0x06>;

clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <0x02>;
bootph-all;
phandle = <0x03>;
};

k3_clks = "/bus@f0000/system-controller@44043000/clock-controller";

| 191 | 0 | DEV_MCASP1_AUX_CLK | CLK_STATE_READY | 96000000 |
| 191 | 1 | DEV_MCASP1_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK | CLK_STATE_READY | 100000000 |
| 191 | 2 | DEV_MCASP1_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK | CLK_STATE_READY | 96000000 |
| 191 | 5 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 |
| 191 | 6 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 |
| 191 | 7 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 |
| 191 | 8 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 |

| 191 | 35 | DEV_MCASP1_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 |
| 191 | 36 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 |
| 191 | 37 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 25000000 |
| 191 | 38 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 |
| 191 | 39 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 |
| 191 | 40 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | CLK_STATE_READY | 0 |
| 191 | 41 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 |
| 191 | 42 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 |
| 191 | 43 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 |
| 191 | 44 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 |
| 191 | 52 | DEV_MCASP1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 |

| 191 | 17 | DEV_MCASP1_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 |
| 191 | 18 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 |
| 191 | 19 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 25000000 |
| 191 | 20 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 |
| 191 | 21 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 |
| 191 | 22 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | CLK_STATE_READY | 0 |
| 191 | 23 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 |
| 191 | 24 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 |
| 191 | 25 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 |
| 191 | 26 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 |
| 191 | 34 | DEV_MCASP1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 |

| 157 | 95 | DEV_BOARD0_MCASP1_ACLKX_IN | CLK_STATE_NOT_READY | 0 |
| 157 | 96 | DEV_BOARD0_MCASP1_ACLKX_OUT | CLK_STATE_READY | 0 |
| 191 | 11 | DEV_MCASP1_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 |
| 191 | 12 | DEV_MCASP1_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 |

| 157 | 99 | DEV_BOARD0_MCASP1_AFSX_IN | CLK_STATE_NOT_READY | 0 |
| 157 | 100 | DEV_BOARD0_MCASP1_AFSX_OUT | CLK_STATE_READY | 0 |
| 191 | 15 | DEV_MCASP1_MCASP_AFSX_PIN | CLK_STATE_READY | 0 |
| 191 | 16 | DEV_MCASP1_MCASP_AFSX_POUT | CLK_STATE_READY | 0 |

0 Suren Porwar 1 month ago in reply to Valerii Repin

TI__Mastermind 30175 points

Hi Valerii,

Can you probe the ACKLR/ACLKX and AFSX/AFSR pins of MCASP on oscilloscope to see the expected values of BCLK and LRCLK.

k3conf dump is not showing any values on ACLKX/FSX?

Also please share the DTS file with PIN controls of MCASP1 , MCASP1 node , and sound node specifically for us to analyze.

Best Regards,

Suren

0 Valerii Repin 1 month ago in reply to Suren Porwar

Prodigy 20 points

Hi Suren.

here is DTS

/dts-v1/;
/plugin/;

/ {
	compatible = "beagle,am67a-beagley-ai", "ti,j722s";
	
	fragment@0 {
		target-path = "/sound";
		__overlay__ {
			status = "disabled"; 
		};
	};
	
	/* ===== Pinmux for McASP1: AXR0=IN, ACLKX/FSX/AXR1/AHCLKX=IN ===== */
	fragment@pins {
		target = <&main_pmx0>;  /* /bus@f0000/pinctrl@f4000 */
		__overlay__ {
			mcasp1_pins_master: mcasp1-pins-master {
				pinctrl-single,pins = <
					0x90 0x00002  /* ... MCASP1_ACLKX (BCLK out) */
					0x98 0x00002  /* ... MCASP1_AFSX  (FS   out) */
					0x8c 0x50002  /* ... MCASP1_AXR0  (Data in)  */
				>;
			};
		};
	};

	fragment@mclk {
		target-path = "/";
			__overlay__ {
			adc5140_mclk: adc5140_mclk {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <12288000>;  /* 12288000 or 24576000*/
			};
		};
	};

	/* simple-audio-card: MCASP1 (CPU) - TLV320ADC5140@4c (Codec) */
	fragment@1 {
		target-path = "/";
		__overlay__ {
			sound_tlv5140: sound_tlv5140 {
				compatible = "simple-audio-card";
				simple-audio-card,name   = "tlv320adc5140-2ch-i2s";
				simple-audio-card,format = "i2s";

				/* CPU is master - generates BCLK/FSYNC */
				simple-audio-card,bitclock-master = <&dailink_cpu>;
				simple-audio-card,frame-master   = <&dailink_cpu>;

				status = "okay";

				dailink_cpu: simple-audio-card,cpu {
					sound-dai = <&mcasp1>;
					system-clock-direction-out;
				};

				simple-audio-card,codec {
					sound-dai = <&tlv320adc5140>;
					/* clocks/clock-names */
				};
			};
		};
	};

	/* Codec TLV320ADC5140 on I2C1 @ 0x4c */
	fragment@2 {
		/*target = <&i2c1>;*/
		target-path = "/bus@f0000/bus@4000000/i2c@4900000";
		__overlay__ {
			#address-cells = <1>;
			#size-cells = <0>;

			tlv320adc5140: tlv320adc5140@4c {
				compatible = "ti,tlv320adc5140";
				reg = <0x4c>;
				#sound-dai-cells = <0>;
				/*
				AVDD-supply = <&vdd_3v3>;
				IOVDD-supply = <&vdd_3v3>;
				DVDD-supply = <&vsys_io_1v8>;
				*/
				clocks = <&adc5140_mclk>;
				clock-names = "mclk";
				status = "okay";
			};
		};
	};

	/* McASP1 as DAI-CPU */
	fragment@3 {
		target = <&mcasp1>;
		__overlay__ {
			status = "okay";
			#sound-dai-cells = <0>;

			pinctrl-names = "default";
			pinctrl-0 = <&mcasp1_pins_master>;

			op-mode    = <0>;  /* 0 = MCASP_IIS_MODE (I2S/TDM framing) */
			tdm-slots  = <2>;
			slot-width = <32>;
			auxclk-fs-ratio = <256>;

			serial-dir = <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>;

			tx-num-evt = <0>;
			rx-num-evt = <0>;
		};
	};
};

here is dump

|   246     |    15    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP1_AFSX_OUT                                             | CLK_STATE_READY     | 0               | 20    | DEV_ATL0_ATL_IO_PORT_AWS_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0                                        | CLK_STATE_READY     | 0               | 32    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP1_AFSX_OUT                                           | CLK_STATE_READY     | 0               | 37    | DEV_ATL0_ATL_IO_PORT_AWS_1_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0                                      | CLK_STATE_READY     | 0               | 55    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP1_AFSX_OUT                                           | CLK_STATE_READY     | 0               | 60    | DEV_ATL0_ATL_IO_PORT_AWS_2_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0                                      | CLK_STATE_READY     | 0               | 72    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP1_AFSX_OUT                                           | CLK_STATE_READY     | 0               | 77    | DEV_ATL0_ATL_IO_PORT_AWS_3_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0                                      | CLK_STATE_READY     | 0               | 95    | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP1_AFSR_OUT                                             | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_PARENT_BOARD_0_MCASP1_AFSX_OUT                                             | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP1_AFSR_OUT                                           | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_1_PARENT_BOARD_0_MCASP1_AFSX_OUT                                           | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP1_AFSR_OUT                                           | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_2_PARENT_BOARD_0_MCASP1_AFSX_OUT                                           | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP1_AFSR_OUT                                           | CLK_STATE_READY     | 0               | | DEV_ATL0_ATL_IO_PORT_BWS_3_PARENT_BOARD_0_MCASP1_AFSX_OUT                                           | CLK_STATE_READY     | 0               | 93    | DEV_BOARD0_MCASP1_ACLKR_IN                                                                          | CLK_STATE_NOT_READY | 0               | 94    | DEV_BOARD0_MCASP1_ACLKR_OUT                                                                         | CLK_STATE_READY     | 0               | 95    | DEV_BOARD0_MCASP1_ACLKX_IN                                                                          | CLK_STATE_NOT_READY | 0               | 96    | DEV_BOARD0_MCASP1_ACLKX_OUT                                                                         | CLK_STATE_READY     | 0               | 97    | DEV_BOARD0_MCASP1_AFSR_IN                                                                           | CLK_STATE_NOT_READY | 0               | 98    | DEV_BOARD0_MCASP1_AFSR_OUT                                                                          | CLK_STATE_READY     | 0               | 99    | DEV_BOARD0_MCASP1_AFSX_IN                                                                           | CLK_STATE_NOT_READY | 0               | | DEV_BOARD0_MCASP1_AFSX_OUT                                                                          | CLK_STATE_READY     | 0               | 0    | DEV_MCASP1_AUX_CLK                                                                                  | CLK_STATE_READY     | 96000000        | 1    | DEV_MCASP1_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK                                        | CLK_STATE_READY     | 100000000       | 2    | DEV_MCASP1_AUX_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK                                       | CLK_STATE_READY     | 96000000        | 5    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                                          | CLK_STATE_NOT_READY | 0               | 6    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                                        | CLK_STATE_NOT_READY | 0               | 7    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                                        | CLK_STATE_NOT_READY | 0               | 8    | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                                        | CLK_STATE_NOT_READY | 0               | 9    | DEV_MCASP1_MCASP_ACLKR_PIN                                                                          | CLK_STATE_READY     | 0               | 10    | DEV_MCASP1_MCASP_ACLKR_POUT                                                                         | CLK_STATE_READY     | 0               | 11    | DEV_MCASP1_MCASP_ACLKX_PIN                                                                          | CLK_STATE_READY     | 0               | 12    | DEV_MCASP1_MCASP_ACLKX_POUT                                                                         | CLK_STATE_READY     | 0               | 13    | DEV_MCASP1_MCASP_AFSR_PIN                                                                           | CLK_STATE_READY     | 0               | 14    | DEV_MCASP1_MCASP_AFSR_POUT                                                                          | CLK_STATE_READY     | 0               | 15    | DEV_MCASP1_MCASP_AFSX_PIN                                                                           | CLK_STATE_READY     | 0               | 16    | DEV_MCASP1_MCASP_AFSX_POUT                                                                          | CLK_STATE_READY     | 0               | 17    | DEV_MCASP1_MCASP_AHCLKR_PIN                                                                         | CLK_STATE_READY     | 0               | 18    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT                                          | CLK_STATE_READY     | 0               | 19    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                          | CLK_STATE_READY     | 25000000        | 20    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                                    | CLK_STATE_READY     | 0               | 21    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                                    | CLK_STATE_READY     | 0               | 22    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT                                    | CLK_STATE_READY     | 0               | 23    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                                 | CLK_STATE_NOT_READY | 0               | 24    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                               | CLK_STATE_NOT_READY | 0               | 25    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                               | CLK_STATE_NOT_READY | 0               | 26    | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                               | CLK_STATE_NOT_READY | 0               | 34    | DEV_MCASP1_MCASP_AHCLKR_POUT                                                                        | CLK_STATE_READY     | 0               | 35    | DEV_MCASP1_MCASP_AHCLKX_PIN                                                                         | CLK_STATE_READY     | 0               | 36    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT                                          | CLK_STATE_READY     | 0               | 37    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT                                          | CLK_STATE_READY     | 25000000        | 38    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT                                    | CLK_STATE_READY     | 0               | 39    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT                                    | CLK_STATE_READY     | 0               | 40    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT                                    | CLK_STATE_READY     | 0               | 41    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT                                 | CLK_STATE_NOT_READY | 0               | 42    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1                               | CLK_STATE_NOT_READY | 0               | 43    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2                               | CLK_STATE_NOT_READY | 0               | 44    | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3                               | CLK_STATE_NOT_READY | 0               | 52    | DEV_MCASP1_MCASP_AHCLKX_POUT                                                                        | CLK_STATE_READY     | 0               | 53    | DEV_MCASP1_VBUSP_CLK                                                                                | CLK_STATE_READY     | 250000000       |

The main question. For recording, pins (clocks) of RX mode are needed. But only playback (TX) clocks are available. It seems so.

0 Suren Porwar 1 month ago in reply to Valerii Repin

TI__Mastermind 30175 points

Hi Valerii,

Are you able to see the BCLK and FSX (Transmit) for playback correctly? Are these not being provided to ADC5140?

If you are able to provide these to ADC correctly, then you would need only AXR[n] data pins configured as INPUT for recording purposes.

Based on your DTS file:

serial-dir = <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>;

I understand you are using AXR0 as receiving data from ADC5140 for recording purposes and thats where AXR0 would be PIN_INPUT

AXR1 is used as transmit used for playback purposes and that would be PIN_OUTPUT.

Hope this helps.

Best Regards,

Suren

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