Part Number: TLV320DAC32
Tool/software:
I have the EVM for this part and I am trying to get it working with some small speakers.
I also have the USB board but I haven't been able to get the software to work (it freezes up on Windows 10 and on Windows 7) so I'm trying to manually control it over the I2C bus instead. The part is detected on the I2C bus and seems to respond as expected.
The problem is that there is no sound coming out the speakers, but also the datasheet has a few things that aren't clear to me so I'd like to have some clarification on a few things just to make sure I'm setting all the registers correctly.
The I2S source can be configured for a 48kHz or 96kHz sample rate.
MCLK = 24.576MHz (regardless of sample rate selected)
LRCLK = 1 during right channel, 0 during left channel
SCLK = bit clock, 1.536MHz at 48kHz sample rate, 3.072MHz at 96kHz sample rate
DATA = 16 bits per channel
I have worked out the following parameters for using SCLK as the clock source and ignoring MCLK:
R=8
P=1
K=8.0 J=8 D=0
DAC Fs = Fsref/1 ??? (seems the higher values are used to eliminate noise at low sample rates so is this correct for my application?)
Use DAC_CLKIN to select PLLDIV_OUT
Apparently PLLCLK_IN / P needs to be >=2MHz and <=20MHz so BCLK PLL can't actually be done at 48kHz as this value would only be 1.536MHz - seems a bit pointless given the popularity of that sample rate, but 96kHz would be in that range so I will use that sample rate initially. Or do I understand that incorrectly?
Then in the register map, I noticed a register for PLL Clock Divider N Value (register 102)
It's not mentioned anywhere else in the datasheet and not in the PLL block diagram. What is this? Does this mean the /8 divider is not fixed? Maybe this should be set to 8?
I've come up with the following data to write
<slave address h18>, <register address h00>, h00, h80, h00, h81, h20, h00, h00, h0a, h00, h04, h00, h08, h00, h17, hc0, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, hc0, h04, h00, hc0, h00, h9c, h00, h00, h00, h80, h00, h00, h80, h0d, h00, h00, h80, h00, h00, h00, h00, h0d, h00, h00, h00, h00, h00, h80, h0d, h00, h00, h00, h80, h00, h80, h0d, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h28
As that didn't work, I decided to try dividing MCLK instead.
Option 2 - MCLK divider at 48kHz or 96kHz sample rate
PLL can be disabled as MCLK only needs to be divided by 8
Q = 16 for 48kHz or 8 for 96kHz
Use DAC_CLKIN to select CLKDIV_OUT
<slave address h18>, <register address h00>, h00, h80, h00, h41, h20, h00, h00, h0a, h00, h04, h00, h08, h00, h17, hc0, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, hc0, h04, h00, hc0, h00, h9c, h00, h00, h00, h80, h00, h00, h80, h0d, h00, h00, h80, h00, h00, h00, h00, h0d, h00, h00, h00, h00, h00, h80, h0d, h00, h00, h00, h80, h00, h80, h0d, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h00, h01, h28
Still no sound
There's a few other things I'm not sure about. How should these be set?:
Routing to HPRCOM?
Output common mode voltage?
DAC bypass - enabled or disabled? Assumed disabled
At the moment, the speakers are connected to the + and - terminals of J12 and J13 of the evaluation kit. Eventually it will be desired to have a headphone jack so what configuration will I need for that?
