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TAD5112-Q1: I2S format and data handling

Kazuki Kuramochi
Genius 10605 points
Part Number: TAD5112-Q1

Tool/software:

Hello Expert,

We understand that it is possible to acquire a Slot:32bit/Word:24bit signal,
but since Slot and Word cannot be set separately, how are the remaining 8 bits treated? Are they ignored?
We would like to know more about the signal acquisition specifications

Best regards,
Kazuki Kuramochi

  • 0
    TI__Mastermind 30891 points

    Hello, when you have a 32bit slot and signal is 24b or 16b  or ... , the reset of bits will be tabbed with zeros.

    Regards,

    Arash 

  • 0 in reply to Arash Loloee
    TI__Genius 10605 points

    Arash-san,


    Based on I2S data format, I think 24bit data input for 32bit slot can work due to this data type is 32bit audio data whose lower 8bit is always 0.
    However, the problem of this point is whether TAD5112-Q1's ASI acquire this lower 8 bit or ignore.
    This is because, if TAD5112-Q1 acquiring lower 8bit data, it will cause unexpected sound if noise is injected during lower 8bit.
    Therefore, we are asking you about how to treat remaining 8bit data on 32bit slot from 24 bit data.

    Do "be tabbed" mean acquiring 8 bit as 0 or ignoring this 8 bit data?

    Best regards,
    Kazuki Kuramochi

  • 0 in reply to Kazuki Kuramochi
    TI__Mastermind 30891 points

    Hello Kuramochi-san,

    Sorry about the confusion here. In this chip, we can set the word width with the register 0x1A ,  bits  PASI_WLEN[1:0] , The slot width is determined by the relationship b/w  BCLK and WCLK as shown below:

    BCLK= # of Ch.  *  Ch/slot  depth  * Fs

    In target mode,  when both BCLK and WCLK are provided, the division of those  will determine the slot width. So if you have a 32bit slot , and you set a 24 bit data mode in the chip, but you sent a 32bit data, it will look at the first 24 bits only, and it does not care about the last 8 bits.

     And if the slot is 32bit, and 32bit data is programmed using (0x1a)  but you send   24bit data, it will add zeros to LSB locations.

    I hope it is clear now. 

    Regards,

    Arash