TAA5212: Register settings for reducing power consumption

Ryu Yamashita

Part Number: TAA5212

Hi team,

Are there any recommended settings for reducing power consumption in the register configuration?
The intended operating conditions are as follows:
Operation Target mode
AVDD 3.3V
IOVDD 1.8V
GPIO Not used
Delay setting Ultra Low Filter
Digital Data LJ
Peripheral I2C
Input 1 channel differential AC input
Other If there is a setting that improves sound quality, they want to set it
They would like to reduce power consumption

Best Regards,
Ryu.

9 months ago

+1 Garret Godfrey 9 months ago

TI__Mastermind 22986 points

Hi Ryu,

Power reduction can be achieved with a 1.8V AVDD or enabling Power Tune Mode by setting register 0x4e to 0xd4 as described in section 6.3.9 on page 55 of the datasheet. Also, here is a power consumption matrix that describes the current draw and performance for different frequency and power tune configurations: https://www.ti.com/lit/an/sbaa609/sbaa609.pdf

Best,

Garret

0 Ryu Yamashita 9 months ago in reply to Garret Godfrey

Genius 4955 points

Hi Garret,

Thank you for your reply.
I understand the power consumption now.
Could you please clarify two additional points?
What effect does changing the “(0x32) PASI_FS_RATE_NO_LIM” register have?
What is the acceptable range for the BLCK/fsync ratio to avoid clock errors?

Best Regards,
Ryu.

+1 Garret Godfrey 9 months ago in reply to Ryu Yamashita

TI__Mastermind 22986 points

Hi Ryu,

The PASI_FS_RATE_NO_LIM allows you to increase the tolerance to 5% on the range for allowable FSYNC frequencies, incorporating a wider range of FSYNC.

Clock errors only occur in case of a change in timing, but the acceptable range of BCLK/fsync ratio should also be 5% if set properly in PASI_FS_RATE_NO_LIM.

You can read more in this app note: https://www.ti.com/lit/an/slaaeg9/slaaeg9.pdf

Best,

Garret

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TAA5212: Register settings for reducing power consumption