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TLV320DAC32: Setting without using MCLK

Ryu Yamashita
Genius 4835 points

Part Number: TLV320DAC32

Hi team,

I'm considering the following settings without using MCLK.
Are there any points I should be careful about in the register settings?
BCLK = 3.072 MHz
Data length = 24 bits
Sampling frequency = 48 kHz

If possible, could you provide the initial register settings?

Best Regards,
Ryu.

  • 0
    TI__Guru 50810 points

    Hi Yamashita-san,

    Unfortunately this will not work. Your BCLK is too small to be the PLL input. See the PLL requirement below from the datasheet.

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Genius 4835 points

    Hi Jeff,

    Does this mean that even when PLLCLK_IN is 3.072MHz and P is 1, it falls outside the conditions?
    Or is the actual calculation formula as follows?
    2MHz ≤ (PLLCLK_IN / (P × N)) ≤ 20MHz

    Does N need to be 2 or greater in this equation?

    Is it correct to think that the red circle symbol represents multiplication?

    Best Regards,
    Ryu.

  • 0 in reply to Ryu Yamashita
    TI__Guru 50810 points

    Hi Yamashita-san,

    My apologies, I misread the formula.

    Your BCLK will be fine, you are correct that if P is 1 (and only 1) your BCLK will work.

    Yes the symbols in the red circle are multiplication. I am not sure why they look like that, but I know the formula represents multiplication.

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Genius 4835 points

    Hi Jeff-san,

    Thank you for your reply.
    Does the value of N not affect this?
    It seems N can only be set starting from 2. It says setting N=0001 results in 17, but is it not possible to set it to 1?

    Best Regards,
    Ryu.

  • 0 in reply to Ryu Yamashita
    TI__Guru 50810 points

    Hi Yamashita-san,

    I don't see any N value on the PLL input in this clock tree.

    There is a NDAC value which controls the divider at the end. Is that what you are thinking of?

    Or are you thinking of the Q value? The Q value has a minimum of 2, but is only used in the non-PLL usecase.

    Best regards,
    Jeff McPherson

  • +1 in reply to Ryu Yamashita
    TI__Guru 50810 points

    Hi Yamashita-san,

    Thank you. I remember now.

    Since this value is not described anywhere in the clock tree, I think it is only intended for advanced use. I don't think you should worry about it.

    I've seen this divider more helpful when the clock is too high compared to too low, and there must be another factor of 2 in the chain because the math of every other use case I've seen does not consider this N value.

    There is an example in the datasheet of using a 3.072MHz clock (MCLK vs BCLK can be muxed)

    2MHz <= 3.072MHz <= 20MHz

    (3.072MHz * 32) / (8 * 256) = 48kHz

    Sorry for the confusion, but you can refer to this example in your use case to confirm that your clocks are achievable with the PLL.

    Best regards,
    Jeff McPherson 

  • 0 in reply to Jeff McPherson
    Genius 4835 points

    Hi Jeff-san,

    Thank you for your response.
    Does the N value not affect the frequency division?
    It did indeed work whether I set N to the default (0010) or to 0001.

    However, stability seems low. Even after sending the configuration data, it doesn't operate. Then, if I touch MCLK or BCLK with my finger, audio output occurs.
    Are there any possible causes?
    Also, should BCLK be applied before configuration, or is it acceptable to apply BCLK afterward?

    Best Regards,
    Ryu.

  • +1 in reply to Ryu Yamashita
    TI__Guru 50810 points

    Hi Yamashita-san,

    I think it's a clock meant for internal use. I don't think it's going to impact your use case.

    When you say you're touching the MCLK or BCLK with your finger, do you mean a wire, a trace, a pad, etc?

    To me that doesn't sound like a PLL configuration problem, but more like a problem with signal integrity of the clock.

    It's normally acceptable to apply BCLK after but I recommend to apply clocks before applying the configuration if possible.

    Best regards,
    Jeff McPherson