TAD5212: Inquiry about allowable BCLK/FSYNC ratio tolerance for TAD5212

Conor

Part Number: TAD5212

Hi,

We are currently evaluating the TAD5212 in our audio system design and have a question regarding the clock error detection and BCLK/FSYNC ratio tolerance.

In the datasheet, we could not find explicit information about the allowable deviation range (tolerance) of the BCLK-to-FSYNC ratio before the device reports a clock error or fails to detect the sampling rate correctly.

Could you please clarify the following points?

What is the allowable tolerance (in %) of the BCLK/FSYNC ratio for the device to operate without a clock error?
Does this tolerance depend on the “Auto sample rate detection mode” or the register setting (PASI_FS_RATE_NO_LIM @ 0x32)?
Are there any internal registers or status flags that indicate when the ratio is out of range?

Thank you very much for your support.
Best regards,

Conor

6 days ago

0 Arash Loloee 5 days ago

TI__Mastermind 31661 points

Hello Conor,

Let me check on allowable tolerance and its dependency and I will update this post by Friday.

bclk to fsync ratio error can be monitored in CLK_ERR_STS1 Register (Address = 0x3D).

Regards,

Arash

+1 Arash Loloee 4 days ago in reply to Arash Loloee

TI__Mastermind 31661 points

Hello Conor,

I verified with the team that the tolerance of the BCLK/FSYNC ratio supports 1% & 5% as well, Default setting is 1% but with PASI_FS_RATE_NO_LIM you can go to 5% tolerance as well.

Tolerance depends on PASI_FS_RATE_NO_LIM setting.

Regards,

Arash

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TAD5212: Inquiry about allowable BCLK/FSYNC ratio tolerance for TAD5212