Part Number: TAS6684-Q1
Hello,
at 7.3.3.9 Class-H Control paragraph of TAS6684 datasheet is mentioned that:
"Configurable max 5ms look-ahead audio signal delay buffer, providing capability to fit various applications systems' DC-DC bandwidth and power supply coupling capacitance"
but on register maps I didn't find where this can be set up, could you help me on this?
Thank You
Hi
Please refer to below comments and diagram.
Delay time should be configured base on the response speed of front converter to avoid clipping distortion.
The max delay time is fixed which depends on the size of internal DSP resource. Actually, for some ANC/RNC usage, we hope to short the Class-H delay as small as possible. The max Class-H delay time is limited by the ramp up time of Boost converter.
Peak Hold Time means current max level hold time. When detected a peak signal the hold counter begins to re-count and hold the PWM level.
Peak Decay means the decay rate for each sample.
Peak offset is a hysteresis threshold (it’s a rate of class-H trigged threshold).
Smooth time constant is the alpha smooth. We recommend using external RC to replace this digital smooth (set the smooth value very small).
Max Detect Samples is the samples used during audio signal level detection.
Class-H Margin is used to fine tune threshold and step to leave output margin to avoid music clipping. The lower margin will cause triggering each step threshold earlier, so the too much margin will cause lower battery lifetime extension.
Please refer to below reference configuration, you can adjust related parameter based on this configuration.
BR.
Wei Qiu.
