TAC5111: TAC5111 PLL Error

Mark Featherston

Part Number: TAC5111

We are observing the following error bits and would like to understand the possible causes for these:

Bit 6 in INT_LIVE0 – Indicates interrupt due to PLL lock.

We have referred to Section 4, “Determination of Incoming Timing in Auto-Detected Mode,” in the TI document SLAAEG9. The register dumps appear correct for our use case, but the above errors are still being reported.

Observed Register Values:

PASI_SAMP_RATE_STS (B0_P0_R62_D[7:2]) = 10100 (20) → Detected Primary FSYNC Rate
PLL_MODE_STS (B0_P0_R62_D[1:0]) = 00 → PLL used in integer modeDEM_RATE_STS (B0_P0_R64_D[7:6]) = 10 (2x) → 2x DEM used for ADC and DAC modulators
FS_CLKSRC_RATIO_DET_MSB_STS (B0_P0_R64_D[5:0]) = 00000 → Audio clock source to FSYNC ratio detected
FS_CLKSRC_RATIO_DET_LSB_STS (B0_P0_R65_D[7:0]) = 00100000 → Audio clock source to FSYNC ratio detected

Could you please share the working register dump of the codec for the following use case:

Codec configured as Slave
Auto Primary BCLK Ratio clock mode
I2S format
16 bits per word

Your inputs on the above error conditions and reference register settings for a known working configuration would be highly appreciated.

Thanks!

11 months ago

0 Mir Jeffres 11 months ago

TI__Mastermind 19690 points

Hi Mark,

Give me a few hours, I will get you a register dump here. PLL lock may be due to your input clocks being incorrect - what clocks are you providing? Are you getting audio in/out successfully? That ratio looks like it is 64, so you are using 32 bit I2S, at 48k? Do you have any drift in the clocking, or can you measure the inputs at the time you are also seeing the interrupt?

Best,
Mir

0 Mir Jeffres 10 months ago in reply to Mir Jeffres

TI__Mastermind 19690 points

Hi Mark,

So sorry to leave you hanging like this. I wrote a script for your configuration and tested it and also had the PLL lock interrupt triggered.

w a0 00 00 # Set page 0
w a0 01 01 # Software Reset
w a0 02 09 # Wake up with AVDD > 2v and all VDDIO level
w a0 10 50 # Configure DOUT as Primary ASI (PASI) DOUT
w a0 1a 40 #i2s, 16 bits
w a0 1e 20 #ch1 left slot 0
w a0 1f 30 #ch2 right slot 0
w a0 32 50 #bin 20 (48k), auto clock config
w a0 34 40 #pasi bclk is input clock source
w a0 37 20 #pasi in target mode (slave mode), multiple of 48k
w a0 38 00 #bclk to fsync ratio = 32 (msb)
# w a0 39 20 #bclk to fsync ratio = 32 (lsb)
w a0 39 00
w a0 50 00 # ADC Ch1 diff input, 5KOhm, 2Vrms ac-coupled, audio band
w a0 55 00 # ADC Ch2 diff input, 5KOhm, 2Vrms ac-coupled, audio band
w a0 76 c0 # Enable Input Ch1 and Ch2, disable output channels
w a0 78 a0 # Power up ADC and MICBIAS


w a0 00 01 #page 1
r a0 34 01 #if 1st msb is 1, clock error, if second, pll lock
r a0 3c 01 #clock then pll lock error, live

It seems like this "PLL Lock" interrupt is triggering when the PLL is locked, which is a good thing! (Phase locked loop). So, if you see this interrupt, it means the PLL is working as it should. The GUI making the interrupt red is misleading.

Let me know if you have more issues.

Best,
Mir

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TAC5111: TAC5111 PLL Error