TAC5111: TAC5111 PLL Error

We are observing the following error bits and would like to understand the possible causes for these:

Bit 6 in INT_LIVE0 – Indicates interrupt due to PLL lock.

 

We have referred to Section 4, “Determination of Incoming Timing in Auto-Detected Mode,” in the TI document SLAAEG9. The register dumps appear correct for our use case, but the above errors are still being reported.

Observed Register Values:

PASI_SAMP_RATE_STS (B0_P0_R62_D[7:2]) = 10100 (20) → Detected Primary FSYNC Rate
PLL_MODE_STS (B0_P0_R62_D[1:0]) = 00 → PLL used in integer modeDEM_RATE_STS (B0_P0_R64_D[7:6]) = 10 (2x) → 2x DEM used for ADC and DAC modulators
FS_CLKSRC_RATIO_DET_MSB_STS (B0_P0_R64_D[5:0]) = 00000 → Audio clock source to FSYNC ratio detected
FS_CLKSRC_RATIO_DET_LSB_STS (B0_P0_R65_D[7:0]) = 00100000 → Audio clock source to FSYNC ratio detected

Could you please share the working register dump of the codec for the following use case:

• Codec configured as Slave
• Auto Primary BCLK Ratio clock mode
• I2S format
• 16 bits per word

Your inputs on the above error conditions and reference register settings for a known working configuration would be highly appreciated.

Thanks!