Part Number: TAS5827
Dear AE team,
We have a few questions about TAS5827 Multi-chip synchronization issues. Thanks for your support.
1.In our array speaker design, three TAS5827 devices share synchronized MCLK, BCLK, and LRCLK, and are configured with identical processing parameters (including RAMP_PHASE_CTRL=0x00) to output 1*180W(2x30W for each TAS5827). We want to achieve perfectly consistent phase alignment in the TAS5827 amplifier on a single device.
Q1: Under this ideal configuration, what are the typical and maximum intrinsic group delay skews among the three chips from digital audio input to analog power output? Do you have relevant measured data or characterization reports?
2. Software Adjustment Mechanism for Output Synchronization
To achieve absolute synchronization at the speaker terminals across multiple channels, we need to finely adjust the audio processing delay of each channel.
Q2: Does TAS5827 support per-channel configuration of a digital audio delay (e.g., in steps of sample cycles) via registers? If yes, please specify the key register address(es), configuration step (e.g., 1/256 sample), and adjustable range.
2. Software Adjustment Mechanism for Output Synchronization
To achieve absolute synchronization at the speaker terminals across multiple channels, we need to finely adjust the audio processing delay of each channel.
· Q2: Does TAS5827 support per-channel configuration of a digital audio delay (e.g., in steps of sample cycles) via registers? If yes, please specify the key register address(es), configuration step (e.g., 1/256 sample), and adjustable range.
3. Best Practices for Multi-Device Synchronization
For acoustic array applications requiring extremely high phase coherence between channels:
· Q3: Beyond ensuring clock synchronization, what is the most recommended hardware connection and initialization sequence (e.g., is it mandatory to use a GPIO for hardware sync triggering)? Regarding register configuration, aside from setting the same PWM phase, which other critical bits must be strictly identical to ensure synchronization?
2. Software Adjustment Mechanism for Output Synchronization
To achieve absolute synchronization at the speaker terminals across multiple channels, we need to finely adjust the audio processing delay of each channel.
· Q2: Does TAS5827 support per-channel configuration of a digital audio delay (e.g., in steps of sample cycles) via registers? If yes, please specify the key register address(es), configuration step (e.g., 1/256 sample), and adjustable range.
3. Best Practices for Multi-Device Synchronization
For acoustic array applications requiring extremely high phase coherence between channels:
· Q3: Beyond ensuring clock synchronization, what is the most recommended hardware connection and initialization sequence (e.g., is it mandatory to use a GPIO for hardware sync triggering)? Regarding register configuration, aside from setting the same PWM phase, which other critical bits must be strictly identical to ensure synchronization?
4. Clarification on the "PWM Phase Synchronization" Feature
The multi-device PWM phase synchronization feature described in the datasheet (setting 45°/90°/135° offsets).
· Q4: Is the design intent of this feature solely for EMI optimization, rather than for acoustic signal alignment? In acoustic array applications, is it explicitly prohibited to enable this feature to avoid introducing destructive fixed delays?
Thanks a lot! Looking forward to hearing from you!
