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TLV320AIC3104: SINAD Issue with TI Audio Codec

Satham Hussaina
Prodigy 40 points

Part Number: TLV320AIC3104

Hi, 

We are using the audio codec IC TLV320AIC3104 in our hardware, and we are facing a SINAD issue. Please provide the ideal values for achieving the best SINAD. 

Register configuration values are below

Enable input path:
i2cset -y -f 0 0x18 17 0x0
i2cset -y -f 0 0x18 18 0x0
i2cset -y -f 0 0x18 19 0x7c
i2cset -y -f 0 0x18 22 0x7c
i2cset -y -f 0 0x18 15 0x0 // PGA volume left ADC
i2cset -y -f 0 0x18 16 0x0 // PGA volume right ADC

Enable output path:
i2cset -y -f 0 0x18 7 0xa
i2cset -y -f 0 0x18 37 0xc0
i2cset -y -f 0 0x18 43 0x0
i2cset -y -f 0 0x18 44 0x0
i2cset -y -f 0 0x18 82 0x80
i2cset -y -f 0 0x18 85 0x80
i2cset -y -f 0 0x18 81 0x80
i2cset -y -f 0 0x18 84 0x80
i2cset -y -f 0 0x18 89 0x80
i2cset -y -f 0 0x18 92 0x80
i2cset -y -f 0 0x18 88 0x80
i2cset -y -f 0 0x18 91 0x80
i2cset -y -f 0 0x18 86 0x09
i2cset -y -f 0 0x18 93 0x09

Please help us resolve this issue. We are in an urgent situation, so we kindly request your prompt and detailed response. 



 Regards,

Satham

  • +1
    TI__Mastermind 19170 points

    Hi Satham,

    Can you send a schematic as well? It would be best to use differential inputs/outputs, and to check on your decoupling capacitors for cleaning up any power supply noise. Please allow me a day to go through your registers.

    -Mir

  • +1 in reply to Mir Jeffres
    Prodigy 40 points

    Hi Jaffres,

      

    Thank you for your response.

    After tuning the register configuration, I am able to achieve the expected SINAD values. However, I am now facing a new issue.

    According to the datasheet, the specified input signal level for single-ended mode is 0.707 VRMS. In my testing, when the input signal exceeds 0.390 VRMS, the SINAD value starts to degrade and extra noise and distraction. Could you please help explain the reason for this behavior and suggest how this issue can be resolved?

    Note: When testing without the ADC/DAC, the SINAD values meet expectations. However, after recording and playback through the ADC/DAC, the SINAD degrades when the input exceeds 0.390 VRMS.

    Looking forward to your guidance.

    Regards,
    Satham

  • +1 in reply to Satham Hussaina
    TI__Mastermind 19170 points

    Hi Satham,

    I just went through your register configuration, and discovered that you are using the left and right PGAs in an analog bypass configuration, sending both to the L and R line outputs. Are you measuring the signal at the analog outputs? If so, maybe it is sending double the signal there, or if you are sending both MIC2L and MIC2R at the same time, they add together to be larger than 0.707Vrms on one ADC/PGA? When happens when you remove the PGA_L and PGA_R routing lines in your register settings, or you just send MIC2L to the PGAs? I will attach the commented script here.

    i2cset -y -f 0 0x18 17 0x0 #mic2l and mic2r are 0db in left adc pga mix
i2cset -y -f 0 0x18 18 0x0 #same for radc pga mic
i2cset -y -f 0 0x18 19 0x7c #ladc powered up, mic1lp/line1lp are single ended in ladc 
i2cset -y -f 0 0x18 22 0x7c #mic1rp/line1rp are single ended, radc powered up
i2cset -y -f 0 0x18 15 0x0 // PGA volume left ADC #ladc pga not muted, gain=0db
i2cset -y -f 0 0x18 16 0x0 // PGA volume right ADC #radc same

Enable output path:
i2cset -y -f 0 0x18 7 0xa #ldac plays ldata, rdac plays rdata
i2cset -y -f 0 0x18 37 0xc0 #l+r dac powered up, hplcom is diferential of hplout
i2cset -y -f 0 0x18 43 0x0 #ldac not muted, dig volume = 0db
i2cset -y -f 0 0x18 44 0x0 #same for rdac
i2cset -y -f 0 0x18 82 0x80 #dac_l1 routed to left-lop/m
i2cset -y -f 0 0x18 85 0x80 #dac_r1 is routed to left_lop/m
i2cset -y -f 0 0x18 81 0x80 #pga_l routed to left_lop/m (analog bypass?)
i2cset -y -f 0 0x18 84 0x80 #pga_r routed to left_lop/m (analog bypass?)
i2cset -y -f 0 0x18 89 0x80 #dac_l1 routed to right_lop/m
i2cset -y -f 0 0x18 92 0x80 #dac_r1 routed to right_lop/m
i2cset -y -f 0 0x18 88 0x80 #pga_l routed to right_lop/m (analog bypass?)
i2cset -y -f 0 0x18 91 0x80 #pga_r routed to right_lop/m (analog bypass?)
i2cset -y -f 0 0x18 86 0x09 #left_lop/m output level=0db gain, not muted, fully powered up
i2cset -y -f 0 0x18 93 0x09 #same for right_lop/m

    Best,
    Mir

  • 0 in reply to Mir Jeffres
    Prodigy 40 points



    We have two configurations:
       1. Codec Loopback without ADC & DAC.

    • Left channel: MIC2L -> PGA -> LEFT_LOP/M
    • Right channel: MIC2R -> PGA -> RIGHT_LOP/M
    1. Record and Playback with ADC & DAC
    • Left channel: MIC2L -> PGA -> ADC -> Audio serial bus -> DAC -> LEFT_LOP/M
    • Right channel: MIC2R -> PGA -> ADC -> Audio serial bus -> DAC -> RIGHT_LOP/M

     

    According to the datasheet, the specified input signal level for single-ended mode supports up to 0.707 VRMS.

    Issue Description:
    When the VRMS is set to 0.390, both Configuration-1 and Configuration-2 work properly, and the SINAD value is as expected, with no noise or distortion observed. However, when the VRMS is increased beyond 0.390, Configuration-1 continues to operate correctly, but in Configuration-2 the SINAD value decreases, and noise and distortion are observed.

    Register Configuration details:

    PGA input
    i2cset -y -f 0 0x18 17 0x0
    i2cset -y -f 0 0x18 18 0x0
    i2cset -y -f 0 0x18 15 0x0 // PGA volume left ADC
    i2cset -y -f 0 0x18 16 0x0 // PGA volume right ADC
    i2cset -y -f 0 0x18 19 0x7c
    i2cset -y -f 0 0x18 22 0x7c

    PGA output
    i2cset -y -f 0 0x18 82 0x00 //DAC L1 disable
    i2cset -y -f 0 0x18 85 0x00 //DAC R1 disable
    i2cset -y -f 0 0x18 84 0x00 //PGA R disable
    i2cset -y -f 0 0x18 81 0x80 //PGA L Enable
    i2cset -y -f 0 0x18 89 0x00 //DAC L1 disable
    i2cset -y -f 0 0x18 92 0x00 //DAC R1 disable
    i2cset -y -f 0 0x18 91 0x00 //PGA R disable
    i2cset -y -f 0 0x18 88 0x80 //PGA R Enable
    i2cset -y -f 0 0x18 86 0x09
    i2cset -y -f 0 0x18 93 0x09

    Before Recording
    i2cset -y -f 0 0x18 37 0x00
    i2cset -y -f 0 0x18 107 0xC0

     

    Playback
    i2cset -y -f 0 0x18 82 0x80 //DAC L1 Enable
    i2cset -y -f 0 0x18 85 0x00 //DAC R1 disable
    i2cset -y -f 0 0x18 84 0x00 //PGA R disable
    i2cset -y -f 0 0x18 81 0x00 //PGA L disable
    i2cset -y -f 0 0x18 89 0x00 //DAC L1 disable
    i2cset -y -f 0 0x18 92 0x80 //DAC R1 Enable
    i2cset -y -f 0 0x18 91 0x00 //PGA R disable
    i2cset -y -f 0 0x18 88 0x00 //PGA R disable
    i2cset -y -f 0 0x18 86 0x09
    i2cset -y -f 0 0x18 93 0x09

    i2cset -y -f 0 0x18 37 0xC0
    i2cset -y -f 0 0x18 107 0x00

    i2cset -y -f 0 0x18 7 0xa
    i2cset -y -f 0 0x18 43 0x01
    i2cset -y -f 0 0x18 44 0x01

    We would like to understand whether any additional register configuration or register tuning is required to achieve the desired VRMS level in Configuration-2.


    Please guide us on how to resolve this issue. If any additional input is required from our side, please let us know. We can also have a mobile discussion if required.

    Mobile no: 9739664268

    Regards,

    Satham

  • 0 in reply to Satham Hussaina
    TI__Mastermind 19170 points

    Hi Satham,

    I sent you a friend request, you may want to edit your post to remove your info to avoid web scrapers. We can send direct messages and I will send you a meeting link for tomorrow if you would like to talk. I am a bit confused about which registers are for which configuration? These look about the same as the registers you had sent before. 

    Best,
    Mir

  • 0 in reply to Mir Jeffres
    Prodigy 40 points

    Hi Jaffers,

    Thank you for your request.

    Please share the meeting link so we can proceed with the discussion.

    Regards,

    Satham

  • 0 in reply to Satham Hussaina
    TI__Mastermind 19170 points

    Hi, please accept the request so I can DM you, and if you can please make it more clear what script you use for configuration 1, vs which for configuration 2.

  • 0 in reply to Mir Jeffres
    Prodigy 40 points

    Hi Jaffres,

    Sorry, I’m unable to access your friend request. I’m not sure whether this is a website issue or another problem.
    I will share my email address, could you please send the meeting request via email?

    Mail ID: sathamhussaina@iwave-global.com

    Regards,

    Satham

  • 0 in reply to Satham Hussaina
    TI__Guru 51040 points

    Hi Hussaina,

    Today is a U.S. holiday for our team. We can follow up with you tomorrow.

    Thanks for your patience,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 40 points

    Hi Jeff,

      Thank you for your update.

    Hi Jaffres,

    Please let me know when you are planning to schedule the team call.

    Kindly include the below email ID in the meeting invite as well



       Mail ID: 1. sathamhussaina@iwave-global.com
                     2. nachiketh.karanth@iwave-global.com

    Regards,

    Satham.
       


  • 0 in reply to Satham Hussaina
    TI__Mastermind 19170 points

    Sent a message. Closing this thread for now.