Part Number: TAC5112EVM-K
Other Parts Discussed in Thread: TAC5112
We are evaluating the TAC5112 for potential integration in multiple products.
In order to understand the input swing configurations we have performed tests where we have tried the different single-ended configurations shown in Table 7-15 of the datasheet (SLASF24A).
The 1VRMS and 2VRMS simply by switching the value in the dropdown menu of the Record Config tab of PurePath Console.
Additionally, we have tried to test the 0.5 Vrms configuration, by setting AVDD to 1.8V on the J24 jumper of the EVM and manually setting the register value of AVDD_MODE bit from VREF_CFG to 1, as well as VREF_FSCALE of VREF_CFG1 set to 2, via the register map of PurePath Console.
We have injected some constant frequency sine waves on IN1P and IN2P, and observed the output via the AC-MB USB interface and monitoring its spectrum.
We were expecting that by driving the analog input amplitude above the configured input swing Vrms level, it would saturate (visible by all kinds of frequency components besides the test frequency) around the configured level. However, we have observed that in all configurations the saturation occurs slightly above 1Vrms.
We haven't tried driving the inputs above 2Vrms, since that would exceed the analog inputs maximum ratings, as per datasheet.
Can you please clarify if our understanding of the expected behavior is correct and if so, what might be going on with the configuration?
