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TAS2563: Hardware Connection Inquiry with NXP i.MX8MP (I2S and I2C Interface)

David Kim2
Genius 3725 points

Part Number: TAS2563

Hello,

I am reviewing the hardware connection between the NXP i.MX8MP and the TAS2563 for a new audio project. I would like to verify if the proposed pin mapping in the attached image is correct and if there are any specific hardware strap settings required.

[Proposed Connection Details]

  • Audio Interface (SAI3 to I2S/TDM):

    • i.MX8MP SAI3_MCLK → TAS2563 FSYNC

    • i.MX8MP SAI3_TXC → TAS2563 SBCLK1

    • i.MX8MP SAI3_TXD → TAS2563 SDIN1

    • i.MX8MP SAI3_RXD ← TAS2563 SDOUT1 (For IV sense feedback)

  • Control Interface (I2C2):

    • i.MX8MP I2C2_SDA ↔ TAS2563 SDA_MOSI

    • i.MX8MP I2C2_SCL ↔ TAS2563 SCL_SELZ

  • Control GPIO:

    • i.MX8MP GPIO → TAS2563 SDZ (Shutdown Control)

[Questions]

  1. I2C Mode Selection: Since the SDA/SCL pins are shared with the SPI interface, what are the specific hardware pin settings (e.g., ADDR0, ADDR1, or other strap pins) required to ensure the device operates in I2C mode?

  2. MCLK-less Operation: Does the TAS2563 support operation using only BCLK/FSYNC from the i.MX8MP without a dedicated MCLK signal?

  3. Voltage Level: If the i.MX8MP I/O voltage is 1.8V, should IOVDD of the TAS2563 also be tied to 1.8V for direct connection?

  4. Pin Mapping Review: Does the overall mapping shown in the attached image look correct for a standard I2S/TDM application with IV sense?

I have attached a screenshot of the mapping for your reference. Looking forward to your expert advice.

image.png

Best regards,

  • 0
    TI__Guru** 114535 points

    Hi David,

    • SAI3_TXFS should be connected to FSYNC
    • Follow the data sheet and user's guide description to configure the device in I2C mode
      • SPII2C_MISO pin shorted to GND
      • Select I2C address through ADDR_SPICLK pin, usually this is shorted to GND to select 0x98 address
    • Yes, TAS2563 supports MCLK-less operation. SBLCK is used as main clock source
    • Yes, select 1.8V on TAS2563 EVM if the host controller is 1.8V
    • Is the image only the table shared above? If that's the case, you just have to adjust the FSYNC connection.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0 in reply to Ivan Salazar
    Genius 3725 points

    Hi Ivan

    Thank you for your support.

    I have designed a circuit using the TAS2563RPPR and attached the schematic for your review. The design was implemented based on the document.

    I would appreciate your feedback on the following points:

    1. Schematic Review: Please review the overall hardware connections in the attached schematic and let me know if there are any issues or areas for improvement.

    2. Internal Boost Mode (4Ω Speaker): We are planning to use a 4Ω / 3W speaker. According to the current configuration, the internal boost mode is expected to deliver approximately 6.1W to a 4Ω load. Will using a 3W speaker with this 6.1W output pose any operational or reliability issues for the IC?

    3. External Boost Mode for 10W Output: To achieve a 10W output, we are considering an External Boost Mode configuration. Specifically, we plan to:

      • DNP (Do Not Populate) L10 (Boost Inductor).

      • Apply 12V directly to PVDD.

      • Use a 4Ω / 10W speaker. Are there any concerns or specific setting requirements when operating the TAS2563 in this external 12V PVDD mode?

    4. Power Supply (VBAT): Is it acceptable to use a DC-DC Buck converter output for the VBAT supply? Are there significant concerns regarding switching noise, or is it highly recommended to use an LDO output for specific power inputs (such as VBAT or IOVDD) to ensure audio performance?

    I look forward to your professional technical guidance.

    Audio_TAS2563RPPR_v1_20260330.pdf

    Best regards,

  • 0 in reply to David Kim2
    TI__Guru** 114535 points

    Hi David,

    1. Schematic review:
      1. Consider replacing C211 and C255 with 35V rated caps as suggested in TI design guidelines.
      2. In TI design guidelines pin1 is connected to VDD and pin 17 to IOVDD, this is to make layout easier. In your schematic there are B114 and B115 components, what is the purpose of these? Are these supposed to be placed between the device and the voltage source?
    2. No concern from TAS2563 perspective, you may just want to verify that speaker is not damaged due to higher power than rated 3W.
    3. This approach is correct for external PVDD mode. Register settings are different for boosted and external power mode, but hardware-wise this is complete.
    4. The high PSRR spec of TAS2563 should allow the device to operate with buck converter, just make sure the buck is able to provide enough current for TAS2563 power requirements.

    You may have these documents already; just want to make sure you look at them:

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0 in reply to Ivan Salazar
    Prodigy 10 points

    Thank you for your reply.
    I have made the modifications as you suggested.
    1-a. Changed C211 and C255 to 35V products.
    1-b. Deleted B114 and B115.
    Additionally, pins 1/17/8 of the TAS2563RPPR are listed as 'No Connect' in the Pin Function settings. Is there a specific reason why they are connected to Power and GND?
    (Were these pins connected to Power/GND to facilitate PCB routing?)
    Please review this.

  • 0 in reply to Seungyeob YI
    TI__Guru** 114535 points

    Hi Seungyeob,

    Thanks for adding the changes to the schematic, these are OK.

    You're correct regarding pins 1/17/8. These were connected to power and GND for PCB layout purposes only, these are not connected internally so can be either left floating or shorted to nearby pins.

    Best regards,
    -Ivan Salazar
    Applications Engineer