TAS5717: Error Status Register

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Hi Rayna,

Thank you for your questions regarding the TAS5717 Error Status Register. 

1. What kind of issue will lead to PLL Autolock error? What's the definition of this error?

• Definition:​ The PLL Autolock Error (typically bit 0 or 1 in the error register, depending on the specific variant) indicates that the Phase-Locked Loop (PLL) circuit failed to achieve or maintain a stable lock onto the incoming clock signal (usually the MCLK or SCK input).

• Leading Issues:

  • Clock Signal Loss:​ The MCLK/SCK input is missing, disconnected, or has dropped below the minimum threshold.

  • Incorrect Clock Frequency:​ The input clock frequency is outside the range supported by the configured PLL settings (e.g., wrong Master Clock frequency for the chosen Sample Rate).

  • Unstable Clock Source:​ Excessive jitter or noise on the clock line preventing the PLL from stabilizing.

  • Configuration Mismatch:​ Incorrect register settings for the PLL (e.g., wrong PLL divisor values), meaning the chip is trying to lock to a frequency that the hardware cannot generate.

Hi Rayna,

2. what is the threshold of overvoltage error?

The overvoltage error is triggered when the PVDD supply voltage exceeds the absolute maximum rating specified in the datasheet. For the TAS5717, the typical threshold for the overvoltage protection (OVP) circuit is around 26–28V​ (please refer to the “Absolute Maximum Ratings” and “Electrical Characteristics” tables in the datasheet for exact values). Once triggered, the device will typically mute the output or enter a protective shutdown to prevent damage.

Hi Rayna,

3. Will the device shutdown once error bit is set? what's the suggestion about software dealing with error register? should customer read error register constantly and write to 0 when error bit is set to confirm whether it's a persistent error?   

• Shutdown Behavior: Not all errors cause immediate shutdown. Some errors (like PLL unlock) may only trigger a mute or warning state, while critical faults (like overvoltage or overtemperature) may initiate a hardware shutdown. The specific response per error flag is detailed in the “Error Status Register” section of the datasheet.

• Software Handling: It is recommended to periodically poll the Error Status Register (e.g., during idle periods or via interrupt-driven routines) to monitor for faults. When an error bit is set:

  a. Log the error and its context (PVDD voltage, temperature, clock status, etc.) for diagnostics.

  b. Clear the error bit by writing 1 to the corresponding bit position (if the register is clear-on-write).

  c. Monitor if the error reoccurs. If it persists, investigate hardware/clock integrity.

  d. Implement a recovery routine (e.g., resetting the device, re-initializing registers) for non-critical errors.

• Persistent Error Confirmation: Yes, we recommend clearing the error bit after reading and then monitoring if it returns. This helps distinguish between transient events (e.g., noise glitch) and persistent faults requiring hardware intervention.