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TAS5782M: 3 wire infterface issue

Toshiro Imi
Expert 7660 points

Part Number: TAS5782M

Hello,

Our customer is facing on a critical issue in TAS5782M 3 wire interface configuration following to the e2e thread below.

https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1601363/tas5782m-3-wire-pcm-with-keeping-4-wire-hard-ware-configuration?tisearch=e2e-sitesearch&keymatch=tas5782m

Then he has some questions about system clock and LRCK/FS relationship changes more than +/-5 MCLK case that is described in the datasheet "9.3.3.5 Serial Audio Port - Data Formats and Bit Depths" in below.

If the relationship between LRCK/FS and system clock changes more than ±5 MCLK, internal operation is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK/FS and system clock is completed.

Q-1 :  How does the customer set the "system clocks" wretten in bold ?

Q-2 :  Is this function able to disable by resister bit ?

Best regards,

  • 0
    TI__Expert 3840 points

    Hi Toshiro,

    I'll check on this and get back to you soon.

    Regards,

    Isaac

  • 0 in reply to Isaac Buliva
    TI__Expert 3840 points

    Hi Toshiro,

    The system clock is the same as MCLK and is applied at the MCLK input, as described in section 9.3.3.3 of the datasheet. For your second question are you asking if system clock can be disabled by writing an I2C register value? You can refer to MCLK in the datasheet for more detailed information on this.

    Regards,

    Isaac 

  • 0 in reply to Isaac Buliva
    TI__Expert 7660 points

    Hi Issac,

    Could you tell us how we can set up system clock or MCLK if he takes 3 wire interface ?

    Which  register the sytem clock disable ? Does he have to disable PLL in this case ?

    (back ground)

    Ever since the customer configured 3 wire interface connecting with MCLK (shown in below e2e thread), he is facing on a faulre by suspended audio output and it seems to come from MCLK or system clock error.

    https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1601363/tas5782m-3-wire-pcm-with-keeping-4-wire-hard-ware-configuration?tisearch=e2e-sitesearch&keymatch=tas5782m

    in order to clarify the root cause, he needs to know an information posted on this thread.

    regards,

  • 0 in reply to Toshiro Imi
    TI__Expert 3840 points

    Hi Toshiro,

    Why is MCLK being connected if 3-wire interface is used and you plan to disable it regardless? Which specific register read-backs are showing the error is on MCLK or system clock? There are several registers that relate to MCLK, including register 4, 13, 14, 15, and 37 to name a few. You can disable MCLK detection as well as disable it as a source for other internal clocks. The register map in the datasheet as the full details on this if you search "MCLK" in the datasheet reg map section.

    Regards,

    Isaac

  • 0 in reply to Isaac Buliva
    TI__Expert 7660 points

    Hi Issac,

    Which specific register read-backs are showing the error is on MCLK or system clock?

    -> I try to let you know his register setting and the result in below. 

    1) He read 0x5B (register 91) DTSR=00h when audio output suspended, even though he sets 06h (256 x fs). Then after that, these resister returned to 06h (256 x fs).
    2) Same thing is happened even though he sets 0x25 (register 37) to 0x18 (ignore MCLK detection, ignore MCLK halt detection).
    3) when audio signal suspended is happened, he read 0x5F (register 95) "clock error not occured".
    4) in addtion he could see same issue even though he sets 0x25 (register 37) to DCAS=1b (disable), same thing is happened.

    in addtion, we need to make sure that we could not disable following function by register setting ?

    If the relationship between LRCK/FS and system clock changes more than ±5 MCLK, internal operation is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK/FS and system clock is completed.

    regards,

  • +1 in reply to Toshiro Imi
    TI__Expert 3840 points

    Hi Toshiro,

    The device has an internal PLL that is used to take either MCLK or SCLK and create the higher rate clocks required by the DSP and the DAC clock, you can readback the registers mentioned in my earlier reply to ensure that sourcing for these clocks is not referencing externally supplied MCLK.
    The "system clock" can refer to the "PLL as master clock" if 3 wire mode is used as described in section 9.3.3.4 "Clock Slave Mode with SCLK PLL to Generate Internal Clocks (3-Wire PCM)". 

    Regards,

    Isaac