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TLV320AIC3204

Jeramie Bianchi
Expert 3315 points

I've noticed that when I have no audio input coming in, I end up getting a digital output value of hex B10x (lower 4 bits are noise).

I’m wondering why might the digitized value of no input signal be more than half the total amplitude?  I would have expected to see something like hex 000x.  Is there some kind of ground clamp that needs to be enabled?

Regards,

Jeramie

  • 0
    TI__Expert 4645 points

    Jeramie, 

    Is this a recording configuration you have on AIC3204? (Analog Input and I2S output?)

    Are you using AIC3204EVM_K? 

    Could you send me the configuration script you used to program AIC3204? 

    Regards,

    Hui

  • 0 in reply to Hui.Li
    TI__Expert 3315 points

    Hi Hui,

    Thanks for the response.

    This is actually for a customer using the AIC3204, and they are using it with analog input and I2S output.

    They have their own setup built, which I have schematic for. I have worked with Jorge to get the inital script setup, but I have not got his script since he went further with the design as it was working so far until this question came up.

    I will get the updated script and we can discuss further.

    Thanks,

    Jeramie

  • 0 in reply to Jeramie Bianchi
    TI__Expert 3315 points

    Codec Script for Reference

    Fullscreen 5824.Codec_Script.txt Download 
    # Setup script for TLV320AIC3204
#
# I2C device address is assumed to be 0x30
#
# Command format consists of:
#
# w aa dd
# w 	= I2C write
# aa 	= hex register address
# dd	= hex data to be written
#
###############################################
# Software Reset
###############################################
#
# Select Page 0
w 00 00
#
# Initialize the device through software reset
w 01 01
#
###############################################



###############################################
# Configure Power Supplies
###############################################
#
# Select Page 1
w 00 01
#
# Power up AVDD LDO
w 02 a9
#
# Disable weak AVDD in presence of external
# AVDD supply
w 01 08
#
# Enable Master Analog Power Control
# Power up AVDD LDO
w 02 a1
#
# Set the input power-up time to 3.1ms (for ADC)
w 47 32
#
# Set the REF charging time to 40ms
w 7b 01
#
###############################################



###############################################
# Clock and Interface Settings
# ---------------------------------------------
# The codec receives: MCLK = 12MHz,
# The codec outputs:
# - BLCK = 3.072 MHz
# - WCLK = 48 kHz
###############################################
#
# Select Page 0
w 00 00
#
# PLL_clkin = MCLK, codec_clkin = PLL_CLK
w 04 03
#
# PLL on, P = 1, R = 1
w 05 91
#
# J = 7
w 06 07
#
# D = 560 (MSB)
w 07 02
# 
# D (LSB)
w 08 30
#
# NDAC = 5, divider powered on
w 0b 85
#
# MDAC = 3, divider powered on
w 0c 83
#
# DOSR = 128 (MSB)
w 0d 00
#
# DOSR (LSB)
w 0e 80
#
# NADC = 5, divider powered on
w 12 85
#
# MADC = 3, divider powered on
w 13 83
#
# AOSR = 128
w 14 80
#
# BDIV_CLKIN = DAC_MOD_CLK
w 1d 01
#
# BCLK N = 2, powered
w 1e 82
#
# BCLK/WCLK are outputs
w 1b 0c
#
###############################################


###############################################
# Configure Processing Blocks
###############################################
#
# Select Page 0
w 00 00
#
# PRB_P2 selected
w 3c 02
#
# PRB_R2 selected
w 3d 02
#
###############################################


###############################################
# Configure ADC Channel
###############################################
#
# Select Page 1
w 00 01
#
# Route IN1L to LEFT_P with 20K input impedance
w 34 80
#
# Route CM1L to LEFT_M with 20K input impedance
w 36 80
#
# Route IN1R to RIGHT_P with 20K input impedance
w 37 80
#
# Route CM1R to RIGHT_M with 20K input impedance
w 39 80

#Setup microphone input
#w 34 10
#w 36 40
#w 37 10
#w 39 40

# MicPGA_L = 0dB
w 3b 00
#
# MicPGA_R = 0dB
w 3c 00
#
# Select Page 0
w 00 00
#
# Power up LADC/RADC
w 51 c0
#
# Unmute LADC/RADC
w 52 00
#
###############################################


###############################################
# Configure DAC Channel
###############################################
#
# Select Page 1
w 00 01
#
# De-pop: 5 time constants, 6k resistance
w 14 25
#
# Route LDAC/RDAC to HPL/HPR
w 0c 08
w 0d 08
#
# Route LDAC/RDAC to LOL/LOR
w 0e 08
w 0f 08
#
# Power up HPL/HPR/LOL/LOR
w 09 3c
#
# Unmute HPL driver, 0dB Gain
w 10 00
#
# Unmute HPR driver, 0dB Gain
w 11 00
#
# Unmute LOL driver, 0dB Gain
w 12 00
#
# Unmute LOR driver, 0dB Gain
w 13 00
#
#
# Select Page 0
w 00 00
#
# LDAC => 0dB
w 41 00
#
# RDAC => 0dB
w 42 00
#
# Power up LDAC/RDAC
w 3f d6
#
# Unmute LDAC/RDAC
w 40 00
#
###############################################

  • 0 in reply to Jeramie Bianchi
    TI__Expert 4645 points

    Hi Jeramie, 

    I could not duplicate this issue using your script. However I do notice that the clock configurations in the script is a little bit mess up. 

    So i modify the script (mainly the PLL configurations) and test the modified script on the AIC32x4 EVM. When I don't provide any analog input signal. I only see noise level output at the digital output (DOUT). 

    please find the attached for the modified script. 

    Regards,

    Hui