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Multirate processing with TLV320AIC3254, additional decimation and programmatic AGC preamp control?

Ondra Kolonicny
Prodigy 20 points

Other Parts Discussed in Thread: TLV320AIC3254, PUREPATHSTUDIO

Hello.

We are designing a SSB receiver using the Weaver method with the
TLV320AIC3254 part. Our system relies greatly on properties of the ADC
decimation fiters and the decimation filter A seems to fit the bill
for us with sampling frequency of 44100 sampels per second. We would
greatly benefit from being able to implement further low pass
filtering & decimation on the miniDSP as the SSB channel is only 3kHz
wide and centered around zero frequency. Therefore further 4x
decimation will improve system noise and lower current consumption. Is
there a way to implement multirate processing on the miniDSP with
PurePathStudio? Is there a way to insert a 2nd decimation block into
PPS? Could an additional low pass filtering & decimation block be
provided to further versions of PPS?

We would also like to utilize the ADC preamp and DRC blocks to
implement automatic volume control for the radio. While the two blocks
work well on their own, they don't know about each other's action. We
would like to control the two synchronously. Is there a way to control
the ADC preamp gain from the miniDSP programatically apart from the
standard AGC block?

Thanks, Ondra

  • 0
    TI__Guru**** 189401 points

    Hi, Ondra,

    Sorry for the delay in getting back to you.

    Were you able to get this resolved?

    -d2

  • 0 in reply to Don Dapkus
    Prodigy 20 points

    Hello Don.

    The issue is still open. We would be thankful for an advice.

    In addition, we found couple of more riddles to be answered.

    We are designing a 12 pole inverse Chebyshev low pass filter for
    AIC3204/3254 with Matlab. A high order sharp inverse Chebyshev filter
    will lead to resonaces, which in turn lead to a total loss of gain of
    around -50dB if the biquad numinator coefficients are scaled to fit
    the <-1, +1) interval.

    Is there a way to scale the result of the filter up by +50dB with the
    AIC3204? I see the maximum DAC digital volume control is +24dB, which
    accounts to 4 bit left shift.

    Is there a way to scale the data up between the biquad blocks of the
    AIC3204? That is preferable because it maintains dynamic range of the
    fixed point computing chain.

    We may rather decide to go with the AIC3254 and design our own filter
    network with the PurePathStudio instead of using the prebaked
    processing blocks of the AIC3204. In that case I believe the PPS block
    Biquad_Eq would fit the bill, only the documentation of the scaling is
    missing. I see following two undocumented design properties on the
    Properties page of the PPS for the Biquad_Eq block:

    PreShift
    and
    HeadRoom

    and I see undocumented runtime properties: Inst2_EQScale,
    Inst4_EQScale, Inst6_EQScale, Inst8_EQScale, Inst10_EQScale.

    How exactly is the scaling applied to the biquad sections? My best bet
    is, that the Biquad_Eq block is modelled internally by Biquad and
    Shift_Scale blocks, where the chain of the biquads is broken into a
    chain of Biquad modules of lenght two (the last one of length one if
    the total Biquad_Eq length is odd) and there is a Shift_Scale block
    added after each Biquad block with a left shift to amplify by HeadRoom
    and multiply by InstX_EQScale. If there is a PreShift value defined,
    then the last Shift_Scale will left shift by PreShift in addition to
    HeadRoom and there will be a right shift of PreShift before the first
    Biquad block. Is my assumption correct?

    It would be great, if the Biquad_Eq block could be documented
    in more detail in the PPS. It would be also great, if the PPS documentation
    could be updated to indicate properties of the decimation /
    interpolation filters. Extending the PPS documentation would limit the
    amount of frequently asked questions on this forum.

    It is important to us to estimate noise properties and dynamic range
    of our filters we design with the AD3204/3254. We know that the filter
    coefficients are in a Q1.23 format and the data path in Q3.29 format.
    We suppose that the data accumulator has a higher resolution than
    Q3.29. Is this assumption correct? What is the internal resolution of
    the accumulator? When using the Biquad or Biquad_Eq blocks, at which
    points is the internal accumulator resolution rounded to Q3.29 format?

    These implementation details are important to us to be able to decide
    how high Q we can afford with the Biquad sections as the high Q
    sections lead to loss of dynamic range and noise shaping

    Thank you,

    Ondra