Hello community,
our application uses several TAS5704 in bridged mode with the following parameters:
MCLK: 12.288 MHz
LRCLK: 48.000 kHz
SCLK = 64 x LRCLK
Interface format: I2S
The application runs well at room temperature, but below ~15degC we observed perodical droputs (period ~1Hz, width: ~13.5ms) on the output signal.
The phase between the rising edges of MCLK and LRCLK was ~10ns. After we shifted the LRCLK phase-aligned to MCLK, the error probability got lower. After exactly aligning both clks to each other, we see no errors anymore.
We have checked all setup/hold requirements for the serial interface, they are well within the specifications and fully compliant to the datasheet.
Whats going on here? I cannot find any statement in the datasheet that requires MCLK and LRCLK zero-phase-aligned to each other.
I would appreciate feedback as soon as possible.
Thanks and regards,
Bjoern