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I am using Zoom OMAP L138 from LogicPD.
I want to set the sampling frequency of the codec which is AIC3106 to 96kHz.
How is it going to be done. I need to use AIC306 in dual rate mode when it is set to 48kHz.
How about the WCLK which is input from McASP. It is set to 96kHz how the condition for Fsref is going to be satisfied?
regards
You are correct. If the AIC3106 is set to dual rate to achieve 96 kHz, the WCLK must also be set to 96 kHz. If the AIC3106 is salve (WCLK is an input) you will need to check with the processor folks to see how to set the WCLK. You could also set the AIC3106 to master such that the WCLK would become an output, but again you would need to check with the processor folks to make the processor the slave.
I use the AIC3106 as slave with the following settings
But AIC3106 still works at 48kHz.
Any suggestions on the possible cause
ADC/DAC= dual rate enabled
wordsize = 32 bits
MCLK =24576kHz,
BCLK=24576kHz/4 = 6144kHz = 96kHz*2*32
WCLk = 96kHz
PLL is disabled
Q=4
The codec works. It was my tone I was supplying was problematic which led me to think the codec was not set to 9kHz. Sorry about that.
regards
Hello,
I'm trying as well to set fs to 96kHz and have a general question concering the Clock generation. (I'm using Evaluation Module OMAP-l137)
If PLL is disabled, the manual (AIC3106 slas509e.pdf) says fs=CLKDIV_IN/(128*Q). With the aforementioned parameters and CLKDIV_IN=MCLK this gives 48kHz and not 96kHz.
As well in the aic3106 test files (aic3106_loop_linein.c) there is written:
FS = ( AIC3106.MCLK * K ) / ( 2048 * P )
For a FS=[48 kHz] & MCLK=[22.5792 MHz]
48kHz = ( 22.5792 MHz * K ) / ( 2048 * P )
P = 2, K[J.D] = 8.7075
which is the formulation for PLL enabled. The register settings then write
EVMOMAPL137_AIC3106_rset( 3, 0x22 ); <- [PLL=OFF][Q=4][P=2]
EVMOMAPL137_AIC3106_rset( 4, 0x20 );<- [J=8]
EVMOMAPL137_AIC3106_rset( 5, 0x6E );<- [D=7075]
EVMOMAPL137_AIC3106_rset( 6, 0x23 );<- [D=7075]
Now I'm very confused which formulation I have to use, when PLL is off. I want to use AIC3106 in slave mode at 96kHz, with McASP1 in master mode, providing BCLK and WCLK.
I would be glad if someone could explain this to me (absolute beginner)
Best regards
Tobias
Hi
To get the frequencies you are interested, you have 2 options.
(1)-----PLL :enabled,
(2)-----PLL: disabled.
Depending on your MCLK, BCLk, you might achieve different frequencies from these cases.
(1) For PLL-disabled case and MCLK =22.5792MHz (and MCLK is chosen by CLKDIV_CLKIN)
You can obtain with Q=2
Fsref = (22579200/2)/256 =44100Hz
Then by setting dual rate enabled --- CODEC_FINST(codecPage0Regs.DATAPATH_SETUP, DATAPATH_SETUP_ADC_DUALRATE, ENABLE); ---
you can get ADC_Fs = 44100/0.5 = 88200Hz; DAC_FS = 44100/0.5 = 88200Hz;
So you cannot get 96000Hz with MCLK =22.5792MHz when PLL is disabled
(2) --PLL enabled
FS = ( 22579200* K ) / ( 2048 * P )
P = 2, K[J.D] = 8.7075 ; R= 1
Fsref=48 kHz
Dual rate enabled
Hence, Nadc= Ndac= 0.5 ==> you can get ADC_Fs = 48000/0.5 = 96000Hz; DAC_FS = 48000/0.5 = 96000Hz
======================================
So for you 2nd case seems OK (and maybe the only option)
Regards
Hello and thank you for your quick reply!
In fact I'm interested in the highest possible frequency, which is 96kHz for the AIC3106. Since I'm not sure how to change the Master Clock, I will try both of your examples.
I'm not really into this stuff so I take the liberty to ask some additional (and perhaps stupid) questions:
- where does the formulation MCLK/(256*Q) you have used comes from? In the manual I read MCLK/(Q*128)
- your example (2) with PLL seems to be the same used in the example i took from the aic3106 test files (see my previous post). Why can PLL be disabled in register 3?
- what is dual rate?
- which role plays the word size in this case?
Sorry to bother you with theses questions, but it would be very useful to understand a bit more what is going on. For me as a mechanical engineer, the manuals read somtimes like a foreign language...
Best regards an thanks in advance
Tobias
Hi
I dont think you can change MCLK since it is coming from crystal.
So you need to go for the 2nd option..
Setting codec frequency can be easily understood from Fgiure 26 in TLV320AIC3106 manual.
AIC3106 needs to generate a reference clock, Fsref, to do the sampling and analog conversion. This is the core point.
This clock is Fsref and it can be generated in 2 ways (i)PLL enabled and (ii)PLL disabled.
--- where does the formulation MCLK/(256*Q) you have used comes from? In the manual I read MCLK/(Q*128)
This is PLL disabled case. For this you need to trace the signal from CLKDIV_IN to CODEC_CLK.
CLKDIV_IN is MCLK (by choosing that in CLKDIV_CLKIN). MCLK is multiplied by 2/Q as you see in that path first. Then this clock which CLKDIV_OUT is used to generate Fsref which is always CLKDIV_OUT / 256 (or PLLDIV_OUT/256 if you choose PLL output by CODEC_CLKIN). Therefore MCLK*2/Q = 256*Fsref
from which we get Fsref = (MCLK*(2/Q))/256 =MCLK/ (128*Q)
--what is dual rate? The easy answer is that it is the case for Ndac=0.5 and Nadc=0.5 which multiply Fsref by 2 to generate ADC_FS and DAC_FS
Try to implement PLL enabled case for 96kHz..
I can try to send some sample codes tomorrow.
regards
- where does the formulation MCLK/(256*Q) you have used comes from? In the manual I read MCLK/(Q*128)
Thank you for your detailed answer!
Some samples would be great, my code is still not working at 96kHz...
Best regards
Tobias
Hi
I think it is not possible (or that easy to me) to use AIC3106 at Fs=96kHz on EVmL137. The thing is that if you use AIC3106 as slave you need to generate bit clock which must be Fs*2*WordLength which is 3072000 for Fs=96000 and WordLength=16. This will be the BCLK which would be generated on MCASP. But MCLK 22579200 is not divisible by 3072000. Therefore you can run AIC3106 at 96kHz. But it is OK and easy to run at Fs=88200
The following setup does that.
Have a go.
On codec side PLL is disabled, double rate enabled. On McASP side 22579200 is divided by 8 to generate 88200*16*2 = 2822400.
So Fs would be 88200Hz.
/* Configure AIC3106 */ EVMOMAPL137_AIC3106_rset( AIC3106_PAGESELECT, 0 ); // Select page 0 EVMOMAPL137_AIC3106_rset( AIC3106_RESET, 0x80 ); // Reset AIC3106 /* ------------------------------------------------------------------------ * * * * AIC3106 Setup * * * * AIC3106.MCLK = PLL1705.SCK02 * * FS = ( AIC3106.MCLK * K ) / ( 2048 * P ) * * * * For a FS=[48 kHz] & MCLK=[22.5792 MHz] * * : 48kHz = ( 22.5792 MHz * K ) / ( 2048 * P ) * * : P = 2, K[J.D] = 8.7075 * * * * ------------------------------------------------------------------------ */
/* Configure AIC3106 registers */ EVMOMAPL137_AIC3106_rset( 3, 0x22 ); // 5 PLL A <- [PLL=OFF][Q=4][P=2] //@@@@@@@@@@@@@@@@@@@ EVMOMAPL137_AIC3106_rset( 4, 0x20 ); // 4 PLL B <- [J=8] EVMOMAPL137_AIC3106_rset( 5, 0x6E ); // 5 PLL C <- [D=7075] EVMOMAPL137_AIC3106_rset( 6, 0x23 ); // 6 PLL D <- [D=7075] EVMOMAPL137_AIC3106_rset( 7, 0x3A ); // 7 Codec Datapath Setup <- [FS=48 kHz][ADC dual rate enabled][DAC dual rate enabled][LeftDAC=LEFT][RightDAC=RIGHT] //@@@@@@@@@@@@@@@@@@@ EVMOMAPL137_AIC3106_rset( 8, 0x00 ); // 8 Audio Interface Control A <- [BCLK=Slave][MCLK=Slave] EVMOMAPL137_AIC3106_rset( 9, 0x00 ); // 9 Audio Interface Control B <- [I2S mode][16 bit] EVMOMAPL137_AIC3106_rset( 10, 0x00); // 10 Audio Interface Control C <- [Data offset=0] EVMOMAPL137_AIC3106_rset( 15, 0x17 ); // 15 Left ADC PGA Gain <- [Mute=OFF][Gain=8.5dB] EVMOMAPL137_AIC3106_rset( 16, 0x17 ); // 16 Right ADC PGA Gain <- [Mute=OFF][Gain=8.5dB] EVMOMAPL137_AIC3106_rset( 17, 0x0F ); // 17 MIC3L/R to Left ADC <- [MIC3L=0dBGain][MIC3R=NotConnect] EVMOMAPL137_AIC3106_rset( 18, 0xF0 ); // 18 MIC3L/R to Right ADC <- [MIC3L=NotConnect][MIC3R=0dBGain] EVMOMAPL137_AIC3106_rset( 19, 0x7C ); // 19 LINE1L to Left ADC <- [SingleEnd][NotConnect][Power=ON][SoftStep=OncePerFS] EVMOMAPL137_AIC3106_rset( 22, 0x7C ); // 22 LINE1R to Right ADC <- [SingleEnd][NotConnect][Power=ON][SoftStep=OncePerFS] EVMOMAPL137_AIC3106_rset( 25, 0x40 ); // 25 MICBIAS <- [MICBIAS=2.0V] EVMOMAPL137_AIC3106_rset( 27, 0 ); // 27 Left AGC B <- [OFF] EVMOMAPL137_AIC3106_rset( 30, 0 ); // 30 Right AGC B <- [OFF] EVMOMAPL137_AIC3106_rset( 37, 0xE0 ); // 37 DAC Power & Output Dvr <- [LeftDAC=ON][RightDAC=ON][HPLCOM=SingleEnd] EVMOMAPL137_AIC3106_rset( 38, 0x10 ); // 38 High Power Output Dvr <- [HPRCOM=SingleEnd][ShortCircuit=OFF] EVMOMAPL137_AIC3106_rset( 43, 0 ); // 43 Left DAC Digital Volume <- [Mute=OFF][Gain=0dB] EVMOMAPL137_AIC3106_rset( 44, 0 ); // 44 Right DAC Digital Volume <- [Mute=OFF][Gain=0dB] EVMOMAPL137_AIC3106_rset( 47, 0x80 ); // 47 DAC_L1 to HPLOUT Volume <- [Routed] EVMOMAPL137_AIC3106_rset( 51, 0x09 ); // 51 HPLOUT Output <- [Mute=OFF][Power=ON] EVMOMAPL137_AIC3106_rset( 58, 0 ); // 58 HPLCOM Output <- [] EVMOMAPL137_AIC3106_rset( 64, 0x80 ); // 64 DAC_R1 to HPROUT Volume <- [Routed] EVMOMAPL137_AIC3106_rset( 65, 0x09 ); // 65 HPROUT Output <- [Mute=OFF][Power=ON] EVMOMAPL137_AIC3106_rset( 72, 0 ); // 72 HPRCOM Output <- [] EVMOMAPL137_AIC3106_rset( 82, 0x80 ); // 82 DAC_L1 to LEFT_LOP/M Volume <- [Routed] EVMOMAPL137_AIC3106_rset( 86, 0x09 ); // 86 LEFT_LOP/M Output <- [Mute=OFF][Power=ON] EVMOMAPL137_AIC3106_rset( 92, 0x80 ); // 92 DAC_R1 to RIGHT_LOP/M Volume <- [Routed] EVMOMAPL137_AIC3106_rset( 93, 0x09 ); // 93 RIGHT_LOP/M Output <- [Mute=OFF][Power=ON] EVMOMAPL137_AIC3106_rset( 101, 0x01 ); // 101 GPIO Control Register B <- [CODEC_CLKIN = CLKDIV_OUT] //@@@@@@@@@@@@@@@@@@@ EVMOMAPL137_AIC3106_rset( 102, 0 ); // 102 Clock Generation Control <- [PLLCLK_IN and CLKDIV_IN use MCLK]
/* Initialize MCASP1 */ mcasp = &MCASP_MODULE_1;
/* ---------------------------------------------------------------- * * * * McASP1 is in MASTER mode. * * BCLK & WCLK come from McASP1 * * DIN is used by write16/write32 * * DOUT is usec by read16/read32 * * * * ---------------------------------------------------------------- */ mcasp->regs->GBLCTL = 0; // Reset mcasp->regs->RGBLCTL = 0; // Reset RX mcasp->regs->XGBLCTL = 0; // Reset TX mcasp->regs->PWRDEMU = 1; // Free-running
/* RX */ mcasp->regs->RMASK = 0xffffffff; // No padding used mcasp->regs->RFMT = 0x00008078; // MSB 16bit, 1-delay, no pad, CFGBus mcasp->regs->AFSRCTL = 0x00000112; // 2TDM, 1bit Rising, INTERNAL FS, word mcasp->regs->ACLKRCTL = 0x000000AF; // Rising INTERNAL CLK,(from tx side) mcasp->regs->AHCLKRCTL = 0x00000000; // INT CLK (from tx side) mcasp->regs->RTDM = 0x00000003; // Slots 0,1 mcasp->regs->RINTCTL = 0x00000000; // Not used mcasp->regs->RCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256
/* TX */ mcasp->regs->XMASK = 0xffffffff; // No padding used mcasp->regs->XFMT = 0x00008078; // MSB 16bit, 1-delay, no pad, CFGBus mcasp->regs->AFSXCTL = 0x00000112; // 2TDM, 1bit Rising edge INTERNAL FS, word mcasp->regs->ACLKXCTL = 0x000000A7; // ASYNC, Rising INTERNAL CLK, div-by-8 // @@@@@@@@@@@@@@@@@@@@@@@@@@@@ mcasp->regs->AHCLKXCTL = 0x00000000; // EXT CLK mcasp->regs->XTDM = 0x00000003; // Slots 0,1 mcasp->regs->XINTCTL = 0x00000000; // Not used mcasp->regs->XCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256
mcasp->regs->SRCTL5 = 0x000D; // MCASP1.AXR1[5] --> DIN mcasp->regs->SRCTL0 = 0x000E; // MCASP1.AXR1[0] <-- DOUT mcasp->regs->PFUNC = 0; // All MCASPs mcasp->regs->PDIR = 0x14000020; // All inputs except AXR0[5], ACLKX1, AFSX1
mcasp->regs->DITCTL = 0x00000000; // Not used mcasp->regs->DLBCTL = 0x00000000; // Not used mcasp->regs->AMUTE = 0x00000000; // Not used
/* Starting sections of the McASP*/ mcasp->regs->XGBLCTL |= GBLCTL_XHCLKRST_ON; // HS Clk while ( ( mcasp->regs->XGBLCTL & GBLCTL_XHCLKRST_ON ) != GBLCTL_XHCLKRST_ON ); mcasp->regs->RGBLCTL |= GBLCTL_RHCLKRST_ON; // HS Clk while ( ( mcasp->regs->RGBLCTL & GBLCTL_RHCLKRST_ON ) != GBLCTL_RHCLKRST_ON ); mcasp->regs->XGBLCTL |= GBLCTL_XCLKRST_ON; // Clk while ( ( mcasp->regs->XGBLCTL & GBLCTL_XCLKRST_ON ) != GBLCTL_XCLKRST_ON ); mcasp->regs->RGBLCTL |= GBLCTL_RCLKRST_ON; // Clk while ( ( mcasp->regs->RGBLCTL & GBLCTL_RCLKRST_ON ) != GBLCTL_RCLKRST_ON );
mcasp->regs->XSTAT = 0x0000ffff; // Clear all mcasp->regs->RSTAT = 0x0000ffff; // Clear all
mcasp->regs->XGBLCTL |= GBLCTL_XSRCLR_ON; // Serialize while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSRCLR_ON ) != GBLCTL_XSRCLR_ON ); mcasp->regs->RGBLCTL |= GBLCTL_RSRCLR_ON; // Serialize while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSRCLR_ON ) != GBLCTL_RSRCLR_ON );
/* Write a 0, so that no underrun occurs after releasing the state machine */ mcasp->regs->XBUF5 = 0; //mcasp->regs->RBUF0 = 0;
mcasp->regs->XGBLCTL |= GBLCTL_XSMRST_ON; // State Machine while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSMRST_ON ) != GBLCTL_XSMRST_ON ); mcasp->regs->RGBLCTL |= GBLCTL_RSMRST_ON; // State Machine while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSMRST_ON ) != GBLCTL_RSMRST_ON );
mcasp->regs->XGBLCTL |= GBLCTL_XFRST_ON; // Frame Sync while ( ( mcasp->regs->XGBLCTL & GBLCTL_XFRST_ON ) != GBLCTL_XFRST_ON ); mcasp->regs->RGBLCTL |= GBLCTL_RFRST_ON; // Frame Sync while ( ( mcasp->regs->RGBLCTL & GBLCTL_RFRST_ON ) != GBLCTL_RFRST_ON );
/* Start by sending a dummy write */ while( ! ( mcasp->regs->SRCTL5 & 0x10 ) ); // Check for Tx ready mcasp->regs->XBUF5 = 0;
/
/*
* Copyright 2008 by Spectrum Digital Incorporated.
* All rights reserved. Property of Spectrum Digital Incorporated.
*/
/*
* AIC3106 Loop Micin
*
*/
#include "evmomapl137.h"
#include "evmomapl137_mcasp.h"
#include "aic3106.h"
static MCASP_Handle mcasp;
/* ------------------------------------------------------------------------ *
* *
* AIC3106 Tone *
* Output a 1 kHz tone through the HEADPHONE/LINEOUT jacks *
* *
* ------------------------------------------------------------------------ */
Int16 aic3106_loop_micin( )
{
Int16 msec, sec;
Int16 sample;
Int32 sample_data = 0;
/* Configure AIC3106 */
EVMOMAPL137_AIC3106_rset( AIC3106_PAGESELECT, 0 ); // Select page 0
EVMOMAPL137_AIC3106_rset( AIC3106_RESET, 0x80 ); // Reset AIC3106
/* ------------------------------------------------------------------------ *
* *
* AIC3106 Setup *
* *
* AIC3106.MCLK = PLL1705.SCK02 *
* FS = ( AIC3106.MCLK * K ) / ( 2048 * P ) *
* *
* For a FS=[48 kHz] & MCLK=[22.5792 MHz] *
* : 48kHz = ( 22.5792 MHz * K ) / ( 2048 * P ) *
* : P = 2, K[J.D] = 8.7075 *
* *
* ------------------------------------------------------------------------ */
/* Configure AIC3106 registers */
EVMOMAPL137_AIC3106_rset( 3, 0x22 ); // 5 PLL A <- [PLL=OFF][Q=4][P=2] //@@@@@@@@@@@@@@@@@@@
EVMOMAPL137_AIC3106_rset( 4, 0x20 ); // 4 PLL B <- [J=8]
EVMOMAPL137_AIC3106_rset( 5, 0x6E ); // 5 PLL C <- [D=7075]
EVMOMAPL137_AIC3106_rset( 6, 0x23 ); // 6 PLL D <- [D=7075]
EVMOMAPL137_AIC3106_rset( 7, 0x3A ); // 7 Codec Datapath Setup <- [FS=48 kHz][ADC dual rate enabled][DAC dual rate enabled][LeftDAC=LEFT][RightDAC=RIGHT] //@@@@@@@@@@@@@@@@@@@
EVMOMAPL137_AIC3106_rset( 8, 0x00 ); // 8 Audio Interface Control A <- [BCLK=Slave][MCLK=Slave]
EVMOMAPL137_AIC3106_rset( 9, 0x00 ); // 9 Audio Interface Control B <- [I2S mode][16 bit]
EVMOMAPL137_AIC3106_rset( 10, 0x00); // 10 Audio Interface Control C <- [Data offset=0]
EVMOMAPL137_AIC3106_rset( 15, 0x17 ); // 15 Left ADC PGA Gain <- [Mute=OFF][Gain=8.5dB]
EVMOMAPL137_AIC3106_rset( 16, 0x17 ); // 16 Right ADC PGA Gain <- [Mute=OFF][Gain=8.5dB]
EVMOMAPL137_AIC3106_rset( 17, 0x0F ); // 17 MIC3L/R to Left ADC <- [MIC3L=0dBGain][MIC3R=NotConnect]
EVMOMAPL137_AIC3106_rset( 18, 0xF0 ); // 18 MIC3L/R to Right ADC <- [MIC3L=NotConnect][MIC3R=0dBGain]
EVMOMAPL137_AIC3106_rset( 19, 0x7C ); // 19 LINE1L to Left ADC <- [SingleEnd][NotConnect][Power=ON][SoftStep=OncePerFS]
EVMOMAPL137_AIC3106_rset( 22, 0x7C ); // 22 LINE1R to Right ADC <- [SingleEnd][NotConnect][Power=ON][SoftStep=OncePerFS]
EVMOMAPL137_AIC3106_rset( 25, 0x40 ); // 25 MICBIAS <- [MICBIAS=2.0V]
EVMOMAPL137_AIC3106_rset( 27, 0 ); // 27 Left AGC B <- [OFF]
EVMOMAPL137_AIC3106_rset( 30, 0 ); // 30 Right AGC B <- [OFF]
EVMOMAPL137_AIC3106_rset( 37, 0xE0 ); // 37 DAC Power & Output Dvr <- [LeftDAC=ON][RightDAC=ON][HPLCOM=SingleEnd]
EVMOMAPL137_AIC3106_rset( 38, 0x10 ); // 38 High Power Output Dvr <- [HPRCOM=SingleEnd][ShortCircuit=OFF]
EVMOMAPL137_AIC3106_rset( 43, 0 ); // 43 Left DAC Digital Volume <- [Mute=OFF][Gain=0dB]
EVMOMAPL137_AIC3106_rset( 44, 0 ); // 44 Right DAC Digital Volume <- [Mute=OFF][Gain=0dB]
EVMOMAPL137_AIC3106_rset( 47, 0x80 ); // 47 DAC_L1 to HPLOUT Volume <- [Routed]
EVMOMAPL137_AIC3106_rset( 51, 0x09 ); // 51 HPLOUT Output <- [Mute=OFF][Power=ON]
EVMOMAPL137_AIC3106_rset( 58, 0 ); // 58 HPLCOM Output <- []
EVMOMAPL137_AIC3106_rset( 64, 0x80 ); // 64 DAC_R1 to HPROUT Volume <- [Routed]
EVMOMAPL137_AIC3106_rset( 65, 0x09 ); // 65 HPROUT Output <- [Mute=OFF][Power=ON]
EVMOMAPL137_AIC3106_rset( 72, 0 ); // 72 HPRCOM Output <- []
EVMOMAPL137_AIC3106_rset( 82, 0x80 ); // 82 DAC_L1 to LEFT_LOP/M Volume <- [Routed]
EVMOMAPL137_AIC3106_rset( 86, 0x09 ); // 86 LEFT_LOP/M Output <- [Mute=OFF][Power=ON]
EVMOMAPL137_AIC3106_rset( 92, 0x80 ); // 92 DAC_R1 to RIGHT_LOP/M Volume <- [Routed]
EVMOMAPL137_AIC3106_rset( 93, 0x09 ); // 93 RIGHT_LOP/M Output <- [Mute=OFF][Power=ON]
EVMOMAPL137_AIC3106_rset( 101, 0x01 ); // 101 GPIO Control Register B <- [CODEC_CLKIN = CLKDIV_OUT] //@@@@@@@@@@@@@@@@@@@
EVMOMAPL137_AIC3106_rset( 102, 0 ); // 102 Clock Generation Control <- [PLLCLK_IN and CLKDIV_IN use MCLK]
/* Initialize MCASP1 */
mcasp = &MCASP_MODULE_1;
/* ---------------------------------------------------------------- *
* *
* McASP1 is in MASTER mode. *
* BCLK & WCLK come from McASP1 *
* DIN is used by write16/write32 *
* DOUT is usec by read16/read32 *
* *
* ---------------------------------------------------------------- */
mcasp->regs->GBLCTL = 0; // Reset
mcasp->regs->RGBLCTL = 0; // Reset RX
mcasp->regs->XGBLCTL = 0; // Reset TX
mcasp->regs->PWRDEMU = 1; // Free-running
/* RX */
mcasp->regs->RMASK = 0xffffffff; // No padding used
mcasp->regs->RFMT = 0x00008078; // MSB 16bit, 1-delay, no pad, CFGBus
mcasp->regs->AFSRCTL = 0x00000112; // 2TDM, 1bit Rising, INTERNAL FS, word
mcasp->regs->ACLKRCTL = 0x000000AF; // Rising INTERNAL CLK,(from tx side)
mcasp->regs->AHCLKRCTL = 0x00000000; // INT CLK (from tx side)
mcasp->regs->RTDM = 0x00000003; // Slots 0,1
mcasp->regs->RINTCTL = 0x00000000; // Not used
mcasp->regs->RCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256
/* TX */
mcasp->regs->XMASK = 0xffffffff; // No padding used
mcasp->regs->XFMT = 0x00008078; // MSB 16bit, 1-delay, no pad, CFGBus
mcasp->regs->AFSXCTL = 0x00000112; // 2TDM, 1bit Rising edge INTERNAL FS, word
mcasp->regs->ACLKXCTL = 0x000000A7; // ASYNC, Rising INTERNAL CLK, div-by-8 // @@@@@@@@@@@@@@@@@@@@@@@@@@@@
mcasp->regs->AHCLKXCTL = 0x00000000; // EXT CLK
mcasp->regs->XTDM = 0x00000003; // Slots 0,1
mcasp->regs->XINTCTL = 0x00000000; // Not used
mcasp->regs->XCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256
mcasp->regs->SRCTL5 = 0x000D; // MCASP1.AXR1[5] --> DIN
mcasp->regs->SRCTL0 = 0x000E; // MCASP1.AXR1[0] <-- DOUT
mcasp->regs->PFUNC = 0; // All MCASPs
mcasp->regs->PDIR = 0x14000020; // All inputs except AXR0[5], ACLKX1, AFSX1
mcasp->regs->DITCTL = 0x00000000; // Not used
mcasp->regs->DLBCTL = 0x00000000; // Not used
mcasp->regs->AMUTE = 0x00000000; // Not used
/* Starting sections of the McASP*/
mcasp->regs->XGBLCTL |= GBLCTL_XHCLKRST_ON; // HS Clk
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XHCLKRST_ON ) != GBLCTL_XHCLKRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RHCLKRST_ON; // HS Clk
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RHCLKRST_ON ) != GBLCTL_RHCLKRST_ON );
mcasp->regs->XGBLCTL |= GBLCTL_XCLKRST_ON; // Clk
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XCLKRST_ON ) != GBLCTL_XCLKRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RCLKRST_ON; // Clk
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RCLKRST_ON ) != GBLCTL_RCLKRST_ON );
mcasp->regs->XSTAT = 0x0000ffff; // Clear all
mcasp->regs->RSTAT = 0x0000ffff; // Clear all
mcasp->regs->XGBLCTL |= GBLCTL_XSRCLR_ON; // Serialize
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSRCLR_ON ) != GBLCTL_XSRCLR_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RSRCLR_ON; // Serialize
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSRCLR_ON ) != GBLCTL_RSRCLR_ON );
/* Write a 0, so that no underrun occurs after releasing the state machine */
mcasp->regs->XBUF5 = 0;
//mcasp->regs->RBUF0 = 0;
mcasp->regs->XGBLCTL |= GBLCTL_XSMRST_ON; // State Machine
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSMRST_ON ) != GBLCTL_XSMRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RSMRST_ON; // State Machine
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSMRST_ON ) != GBLCTL_RSMRST_ON );
mcasp->regs->XGBLCTL |= GBLCTL_XFRST_ON; // Frame Sync
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XFRST_ON ) != GBLCTL_XFRST_ON );
mcasp->regs->RGBLCTL |= GBLCTL_RFRST_ON; // Frame Sync
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RFRST_ON ) != GBLCTL_RFRST_ON );
/* Start by sending a dummy write */
while( ! ( mcasp->regs->SRCTL5 & 0x10 ) ); // Check for Tx ready
mcasp->regs->XBUF5 = 0;
/* Play Tone */
for ( sec = 0 ; sec < 5 ; sec++ )
{
for ( msec = 0 ; msec < 1000 ; msec++ )
{
for ( sample = 0 ; sample < 48 ; sample++ )
{
/* Read then write the left sample */
while ( ! ( MCASP1_SRCTL0 & 0x20 ) );
sample_data = MCASP1_RBUF0_32BIT;
while ( ! ( MCASP1_SRCTL5 & 0x10 ) );
MCASP1_XBUF5_32BIT = sample_data;
/* Read then write the left sample */
while ( ! ( MCASP1_SRCTL0 & 0x20 ) );
sample_data = MCASP1_RBUF0_32BIT;
while ( ! ( MCASP1_SRCTL5 & 0x10 ) );
MCASP1_XBUF5_32BIT = sample_data;
}
}
}
/* Close Codec */
EVMOMAPL137_AIC3106_rset( AIC3106_PAGESELECT, 0 ); // Select Page 0
EVMOMAPL137_AIC3106_rset( AIC3106_RESET, 0x80 ); // Reset the AIC3106
/* Close McASP */
mcasp->regs->SRCTL0 = 0; // Serializers
mcasp->regs->SRCTL1 = 0;
mcasp->regs->SRCTL2 = 0;
mcasp->regs->SRCTL3 = 0;
mcasp->regs->GBLCTL = 0; // Global Reset
return 0;
}
That code is given in the attached file
Regards
Thank you!
I tried your example (as linein loop) and it works! Unfortunately I'm not able to store the digital signal to see if the samplingrate has really increased. Probably a simple programming mistake. The code is attached, if you have time to shortly look over it I would be glad.
Best regards and thank you again for your help. The aic3016 codec has become less mysterious to me now :)
Tobias
Hi
To test if Fs is set to 88200Hz, you suplly a sinusoid signal at 44kHz (should be less than 88200/2=44100Hz by Nyquist law) and the observe the playback signal on the osiloscope if you see the same tone at that frequency..
Regards