Other Parts Discussed in Thread: TLV320AIC3254
Hi Guys!
Can someone please clarify me the following: Currently I design I2C control interface on FPGA for TLV320AIC3254. According to the I2C bus spesification SCL line can be controled both by master and slave(slave can keep it low even if master released it - to reduce the speed of transfer). In AIC3254 description pdf file(SLAS549A, I2C control interface section) there is a sentence: "Remember that the master always drives the clock line" - does it mean that codec will not negate SCL line in any condition, and it is superfluous to implement additional logic to support this requirement?
Best regards, Fedor.