Hello, I am using the AIC3204 software. To ensure that I partially understand how to use the board, the software and the CODEC, I connected an audio source to IN1 and piped-it out to the ADC portion. I now have digitized audio on the DOUT pin (TP19). I can also see it clearly with my oscilloscope. Then I simply tied a wire from the DOUT pin TP19 to the DIN pin TP20 and routed the DAC's digitized audio to the HEADPHONE OUT connector using the software and I can hear my audio. I also had to tie a wire between MCLK TP23 and BCLK TP22. Disconnecting either wire (TP22 < -- > TP23 or TP19 < -- > TP20) disables the audio on my speakers therefore, I know that I am in fact using the ADC and the DAC properly.
My question now pertains to the clocking for the DAC. How does it work? In the AIC3204 software, under DIGITAL SETTINGS -> CLOCKS / INTERFACE --> CODEC CLOCK / PLL tab, here's what I have:
In the "Enter Codec Input Clock" box, I entered 3.072 Mhz. The reason for this is prior to having a loop-back audio on the same board, I was using a PCM1803 board and I was feeding the clocks on the AIC3204 board without quite understanding what I was doing. Anyhow, the point here is I will explain what I have at the moment and I'd like to someone to explain why it is working because I don't quite understand (and the documentation is not great).
So, in the "Enter Codec Input Clock" box, I entered 3.072 Mhz. Under it at the bottom, the drop-down box has PLL_CLK. Above in the middle, in the "Enter PLL Input Clock", I entered again 3.072 Mhz and the drop-down beneath it has MCLK. Then, in the (R x J x D) / P section, I entered 4 (R) x 7 (J) x 0 (D) / 1 (P) and I checked the "Power" checkbox. Changing the 3.072 value has absolutely no effect to the quality of the audio.
So, how does this section work? Changing the bottom-left dropdown from PLL_CLK to MCLK changes the audio. But leaving it to PLL_CLK and changing the "Enter PLL Input Clock" value has no effect. The only fields that have an effect are the RJD/P values.
The in the Dividers tab, NDAC and NADC are set to 2 and Power is checked, MDAC and MADC are set to 7 and Power is checked and DOSR and AOSR are set to 128. In the bottom right, the DAC_FS and ADC_FS are set to 48Khz and these values change based on what I change on the Dividers tab.
The last tab I changed is the Audio Interface tab in the Audio Bus Settings section: I2S, 24 bits, BCLK direction is set to INPUT, default polarity and WCLK is set to OUTPUT. Changing the BCLK and WCLK direction boxes removes the audio.
Anyhow, I don't quite understand the Clocks / Interface section and I'd really like someone to perhaps explain why my settings above work.
Thanks.