Other Parts Discussed in Thread: TLV320AIC3204EVM-K
I have the TLV320AIC3204EVM-K development kit and I am using the AIC3204 application to control the EVM. I have questions related to the clocking. I've read the manuals but it is still not enough and they don't answer my questions.
Briefly, my hardware setup consists of a microphone connected to a device with a line-level audio output signal which is connected to IN 1 on the EVM board. Then, I have a headset connected to J9 (HEADPHONE OUT) also on the EVM. Also, this is the important part - in order for me to confirm that my microphone's audio was properly digitized AND that my digitized audio was being properly converted back to analog, I simply put a jumper wire on the EVM board between TP19 (DOUT) and TP20 (DIN) to do a physical loopback externally on the board. Also, I have a jumper wire between TP22 (BLCK) and TP23 (MCLK). Pulling either of these wires will cut the audio in my headset... so, this means the AIC3204 software, in terms of settings, is fine.
In the AIC3204 application, under DIGITAL SETTINGS > CLOCKS / INTERFACE > AUDIO INTERFACE tab, in the left-hand side box, I have I2S, 24bits, BLCK direction = INPUT, BCLK polarity = DEFAULT and WCLK direction = OUTPUT. If I change the "direction" of either BCLK and WCLK, I don't hear the audio.
But this is where my understanding stops and I need help.
So, I know that the 3204 requires a clock input in order for it to serve its purpose of converting audio and the clocking is done via the MCLK pin. Right now, on the USB-MODEVM board, SW2.1, 2.3 and 2.5-7 set to ON and 2.2, 2.4 and 2.8 set to OFF. The ones I am interested in are 2.5 > ON meaning that the MCLK is coming from the TAS1020 and 2.8 > OFF meaning that MCLK comes from what I selected on 2.5 (TAS1020). If I put my oscilloscope on TP23 (MCLK) on the EVM (codec board), I see an approximate frequency of 11.3 Mhz although the TAS1020 crystal is only 6Mhz... so I assume the IC has some sort of frequency multiplier. This clock signal is actually coming from the TAS1020's pin 39 MCLKO1 from what I can see on the schematics.
Question 1: Should this frequency of 11.3Mhz be correct? Or what should be the exact frequency I should be seeing here?
In the AIC3204 application, under DIGITAL SETTINGS > CLOCK / INTERFACE > CODEC CLOCK / PLL tab, what's the purpose of the top-left box where it says "Enter Codec Input Clock" field? I would assume that the value I enter in there would have a direct correlation with the audio "quality" (or how the audio sounds) but I can put 0 just like I can put 2000, it doesn't change the audio. The same goes for the box next to it where it says "Enter PLL Input Clock". I can put any value in here and the audio doesn't change. The only way I can change the audio is if I set the bottom-left drop-down box to MCLK or PLL_CLK. If I set it to MCLK, the audio quality is low but I can still hear everything. If I set it to PLL_CLK, then I must check the POWER box in the PLL section in the middle where I see the calculations for RJD/P. So, if I choose PLL_CLK in the bottom-left and click the POWER checkbox, then I hear very high quality audio.
Question 2: What is the purpose of the "Enter Codec Input Clock" and "Enter PLL Input Clock" fields if putting any value in either boxes does not have any audible effect?
Question 3: Is it because the MCLK frequency is "fixed" by the TAS1020 so I have to take for granted that the frequency is 11.3Mhz and the only reason to put it in there is to make sure I do the proper calculations of RJD/P and the fields on the DIVIDERS tab? Otherwise, shouldn't these fields be grayed-out / disabled?
In the DIGITAL SETTINGS > CLOCK / INTERFACE > DIVIDERS tab, I realize that changing these values has an effect on the audio. But if it is because I need to take for granted that the on-board MCLK is fixed at 11.3 Mhz, should I make my calculations based on that frequency and that frequency only? Or in other words, if I was to supply my own MCLK to the codec instead of using the on-board 11.3 Mhz, I presume that THEN I would have to enter MY clock value in one of the two fields metioned in Q2 above, therefore the values on the DIVIDERS page would change to reflect my own MCLK?
I am confused and lost. I have been trying to understand the clocking scheme for the last week and I've read the multiple documents I have but it is not enough.
Thank you.