Hello,
We have developed a prototype with CC8520 + TLV320AIC3204 and there is just one missing feature to be solved. We could mix the local microphone input from IN3_R&IN_3L+PUREPATH I2S sound to HPR&HPL. However we couldn't find how to do that to output to LOL&LOR output. The LOL&LOR output works great with sound from PUREPATH I2S, but couldn't be mixed with IN3_R&IN3_L. Here is the customization script for slave device (OFF to SR-SWITCH):
# PIN RESET
p Reset 1 # Release the reset pin
# RESET
w 30 00 00 # Select register page 0
w 30 01 80 # I2C reset
# CLOCK SETTINGS
w 30 0B 81 # Power up the NDAC divider with value 1
w 30 0C 82 # Power up the MDAC divider with value 2
w 30 0D 00 # Program OSR for DAC to 128 (MSB)
w 30 0E 80 # Program OSR for DAC to 128 (LSB)
# DIGITAL INTERFACE
w 30 1B 00 # I2S, 16-bit, BCLK and WCLK are inputs
# PROCESSING BLOCK USAGE
w 30 3C 08 # Select DAC processing block PRB_P8
# ANALOG POWER SUPPLY
w 30 00 01 # Select register page 1
w 30 01 08 # Disable internal crude AVDD before powering up the internal AVDD LDO
w 30 02 01 # Enable internal analog LDO, analog blocks powered
w 30 0A 40 # Common mode set to 0.75V
# MICPGA DELAY, REFERENCE CHARGING AND HEADPHONE DE-POP
w 30 47 31 # MICPGA startup delay is 3 ms
w 30 7B 01 # Reference charging time is 40 ms
w 30 14 65 # HP driver power-up: 50 ms soft routing step time, 5.0 time constants, 6k resistance
# Audio input ROUTING from external input connector for mixing with I2S audio
w 30 34 04 # IN3L is rout\ed to Left MICPGA with 10K resistance
w 30 36 40 # CM1L is routed to Left MICPGA via CM1L with 10K resistance
w 30 37 04 # IN3R is routed to Right MICPGA with 10K resistance
w 30 39 40 # CM1R is routed to Right MICPGA via CM1R with 10K resistance
w 30 33 70 # microphone bias from AVDD
w 30 00 00 # Select register page 0
w 30 53 06 # Left ADC Channel Volume = 19.0dB
w 30 43 00 # Headset detection disabled
# AUDIO OUTPUT ROUTING
w 30 00 01 # Select register page 1
w 30 09 3F # Output Driver Power Control Register all enabled
d 1000
w 30 10 00 # HPL driver is not muted
w 30 11 00 # HPR driver is not muted
w 30 12 00 # LOL driver is not muted
w 30 13 00 # LOR driver is not muted
d 1000
w 30 0C 0c # HPL routing: Left channel's DAC reconstruction filter's positive terminal & MAL output is routed to HPL
w 30 0D 0c # HPR routing: Right channel's DAC reconstruction filter's positive terminal & MAR output is routed to HPR
w 30 0E 0a # LOL routing: Left channel's DAC reconstruction filter output & MAL output is routed to LOL
w 30 0F 0a # LOR routing: Right channel's DAC reconstruction filter output & MAR output is routed to LOR
One thing I found out is that register 12 and 13 setting to make the mix to HPL&HPR according to datasheet is 0x0A, but it just mixes with 0x0C.
Thanks,
Gilson
