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How to setup the correct clock configuration for ADC TLV320ADC3101.

Other Parts Discussed in Thread: TLV320ADC3101

Hi, I need a help in setting a correct configuration for TLV320ADC3101. I am using this ADC as a slave and I have got inputs MCLK and BCLK from master. My MCLK is 35MHz. Can anyone guide me with setting a correct audio clocks.

Since I have MCLK present from the master chip. Is it OK to power down the PLL circuit? Also If my sampling frequency is set to be 48KHz, what should be my NADC,MADC and AOSR values? Datasheet does not define these terms clearly. Is there any distinct advantage of using internal PLL for the clock generation? Do I need to set P,R,J,D variable values?

Please advice.

  • Hi,

    If you are using the PLL, I would suggest that you make the ADC3101 the master. Here is an app note that covers this subject:

    http://www.ti.com/lit/an/slaa469/slaa469.pdf

    For advice on the clocking, please see this app note here:

    http://www.ti.com/lit/an/slaa404c/slaa404c.pdf

    Although this document is for a different part, the clock tree for the ADC is the same. The clock tree starts on page 4, just ignore the DAC tree.

  • Hi,

    Thanks for this tip. It means I can power down PLL because the ADC3101 in slave mode. I also do not need to set P,F,D,J values. I assume that I just need to set NADC and MADC value. Considering 44KHz of sampling frequency at MCLK 35MHz, I set MADC =6 and NADC=1. AOSR=128 becasue I use PRB_R1 mode for DSP. Actually is there any way that I can bypass the DSP. I just need ADC conversion and I have seperate DSP for all the audio processing. Can I do that?

    Also,

    Since I do not have EVM with me, How can I do quick check on the functioning of the chip? I can validate the I2C communication since I can toggle GPIO on and off. But when I give the MIC input, I do not see any output coming out.

    Can you help me to verify my register contents?