Hi, I need a help in setting a correct configuration for TLV320ADC3101. I am using this ADC as a slave and I have got inputs MCLK and BCLK from master. My MCLK is 35MHz. Can anyone guide me with setting a correct audio clocks.
Since I have MCLK present from the master chip. Is it OK to power down the PLL circuit? Also If my sampling frequency is set to be 48KHz, what should be my NADC,MADC and AOSR values? Datasheet does not define these terms clearly. Is there any distinct advantage of using internal PLL for the clock generation? Do I need to set P,R,J,D variable values?
Please advice.