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how to set register for DAC operation in LM49350?

Wayne Jeong97575
Intellectual 685 points
Other Parts Discussed in Thread: LM49350

Hello everyone.

We are designing LM49350 on our product and want to use DAC function (Input : PORT1 - I2S, Output : AUX). 

But I am not sure exactly register value for DAC function. 

I use the following clock values​​.  

MCLK : 12.288MHz , Sample rate : 8KHz, CLK : 256KHz, Sync :32KHz

Below picture are the audio path that I want to use.

    

Please, let me know how to set those and if it is possible, can I get example?

Additionally what is S diver exactly?

Thank you.

  • 0
    TI__Genius 13650 points

    Hi Wayne,

    Is it necessary to run SYNC at a different clock frequency from fs? If fs=SYNC=8kHz, CLK=256kHz, MCLK=12.288MHz, and the word length is 16 bit, then I would suggest the following configuration:

     

    SYNC_RATE = 000 (16 clock cycles)

    RX_WIDTH = 011 (16 bit word length)

     

    The DACs must be clocked at 2*OSR*fs, so with the default OSR of 128, it is necessary to divide the 12.288MHz MCLK down to 2048kHz. This can be done by configuring DAC_CLK_DIV to divide by 6. The DAC_CLK_DIV divider is shown as the %S in the datasheet clocking diagram.