Other Parts Discussed in Thread: PCM9211
Will the DIR on the PCM9211 lock to a 48 kHz word clock? From what I could tell it seemed the DIR was meant to recover the clock from an actual SPDIF stream, but I just want the PLL to lock to a word clock.
Overall, what I'm trying to design is an ADC whose sample rate can be set by an external word clock followed by an AES/EBU transmitter. The PCM9211 looked like a good option for this, but the synchronization issue remains unclear.
