Other Parts Discussed in Thread: SRC4382
Hi,
I'm currently designing an interface to control some SRC4382 Sample rate converters over SPI, and I'd like to clarify something in the datasheet regarding User and Channel status insertion. In the Digital Interface Transmitter section (page 28), the datasheet appears to suggest that control register 0x09 is the only register that needs setting to the appropriate source. However, in the control register applications information part of the datasheet (page 55), control register 0x08 has a bit labelled TXBTD which enables/disabled transfers from the User Access buffers to the Transmit buffers.
My initial understanding was that I would be able to update the buffers without driving the TXBTD bit in register 0x08, assuming that I didn't process updates during the Block Start where presumably the buffer transfer occurs? Is this correct, or do I need to explicitly disable and re-enable transfers to the Transmit buffer during each update?
Best regards,
Charles.