Hi
Iam currently using the AIC3106in my custom board. I want to check I2S out from codec.I want codec as I2S master ie BCLK and WCLK as ouput from CODEC. We have connected MIC input in MIC3R. After initializing the codec through I2CSET from command line. i tried to speak through MIC, but iam not getting any clock or digital data out.
Whether my testing is correct? I had attached my register settings?
| Reg No | Reg Description | Value |
| 0x00 | Page select register | 0x0 |
| 0x01 | Software Reset Register | 0x80 |
| 0x02 | Codec Sample Rate Select Register | 0x0 |
| 0x03 | PLL Programming Register A | 0x91 |
| 0x04 | PLL Programming Register B | 0x04 |
| 0x05 | PLL Programming Register C | 0x0 |
| 0x06 | PLL Programming Register D | 0x4 |
| 0x07 | Codec Datapath Setup Register | 0x8A |
| 0x08 | Audio Serial Data Interface Control Register A | 0xC0 |
| 0x09 | Audio Serial Data Interface Control Register B | 0x40 |
| 0x0A | Audio Serial Data Interface Control Register C | 0x0 |
| 0x0B | Audio Codec Overflow Flag Register | 0x01 |
| 0x0C | Audio Codec Digital Filter Control Register | 0x0 |
| 0x0D | Headset / Button Press Detection Register A | 0x0 |
| 0x0E | Headset / Button Press Detection Register B | 0x0 |
| 0x0F | Left ADC PGA Gain Control Register | 0x20 |
| 0x10 | Right ADC PGA Gain Control Register | 0x20 |
| 0x11 | MIC3LR_MIC3 control registers | 0xFF |
| 0x12 | MIC3L/R to Right ADC Control Register | 0xFF |
| 0x13 | LINE1L to Left ADC Control Register | 0x0 |
| 0x14 | LINE2L to Left ADC Control Register | 0x78 |
| 0x15 | LINE1R to Left ADC Control Register | 0x0 |
| 0x16 | LINE1R to Right ADC Control Register | 0x78 |
| 0x17 | LINE2R to Right ADC Control Register | 0x78 |
| 0x18 | LINE1L to Right ADC Control Register | 0x78 |
| 0x19 | MICBIAS Control Register | 0x0 |
| 0x20 | Left AGC Control Register A | 0x0 |
| 0x21 | Left AGC Control Register B | 0xFE |
| 0x22 | Left AGC Control Register C | 0x0 |
| 0x23 | Right AGC Control Register A | 0x0 |
| 0x24 | Right AGC Control Register B | 0xFE |
| 0x25 | Right AGC Control Register C | 0x0 |
| DAC Power and Output Driver Control Register | 0x0 | |
| High-Power Output Driver Control Register | 0x0 | |
| Output Driver Pop Reduction Register | 0x0 | |
| 0x2b | Left DAC Digital Volume Control Register | 0xA8 |
| 0x2c | Right DAC Digital Volume Control Register | 0xA8 |
| 0x2D | LINE2L to HPLOUT Volume Control Register | 0x2F |
| 0x2E | PGA_L to HPLOUT Volume Control Register | 0x2F |
| 0x2F | DAC_L1 to HPLOUT Volume Control Register | 0xAF |
| 0x30 | LINE2R to HPLOUT Volume Control Register | 0x0 |
| 0x31 | PGA_R to HPLOUT Volume Control Register | 0x0 |
| 0x32 | DAC_R1 to HPLOUT Volume Control Register | 0x0 |
| 0x33 | HPLOUT Output Level Control Register | 0x0C |
| 0x34 | LINE2L to HPLCOM Volume Control Register | 0x2F |
| 0x35 | PGA_L to HPLCOM Volume Control Register | 0x2F |
| 0x36 | DAC_L1 to HPLCOM Volume Control Register | 0xAF |
| 0x37 | LINE2R to HPLCOM Volume Control Register | 0x0 |
| 0x38 | PGA_R to HPLCOM Volume Control Register | 0x0 |
| 0x39 | DAC_R1 to HPLCOM Volume Control Register | 0x0 |
| 0x3A | HPLCOM Output Level Control Register | 0x0C |
| 0x3B | LINE2L to HPROUT Volume Control Register | 0x0 |
| 0x3C | PGA_L to HPROUT Volume Control Register | 0x0 |
| 0x3D | DAC_L1 to HPROUT Volume Control Register | 0x0 |
| 0x3E | LINE2R to HPROUT Volume Control Register | 0x2F |
| 0x3F | PGA_R to HPROUT Volume Control Register | 0x2F |
| 0x40 | DAC_R1 to HPROUT Volume Control Register | 0xAF |
| 0x41 | HPROUT Output Level Control Register | 0xC |
| 0x42 | LINE2L to HPRCOM Volume Control Register | 0x0 |
| 0x43 | PGA_L to HPRCOM Volume Control Register | 0x0 |
| 0x44 | DAC_L1 to HPRCOM Volume Control Register | 0x0 |
| 0x45 | LINE2R to HPRCOM Volume Control Register | 0x2F |
| 0x46 | PGA_R to HPRCOM Volume Control Register | 0x2F |
| 0x47 | DAC_R1 to HPRCOM Volume Control Register | 0xAF |
| 0x48 | HPRCOM Output Level Control Register | 0xC |
Kindly suggest me on the testing
Regards
Vijayabharathi C
