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TLV320AIC33 Codec with different sampling rate for A/D and D/A

Eran Hashin
Prodigy 60 points
Other Parts Discussed in Thread: TLV320AIC33

I am using the TLV320AIC33 Codec with different sampling rate for A/D and D/A, using the WCLK and PGIO1 for frame sync.

Wanted to ask how the audio serial data word offset define in register 10 will work in this mode.

As I understand this register defines the offset of valid data from frame sync, but in the case that I have different sampling rates and two different frame syncs, to which frame sync will the offsetrelate, to WCLK or PGIO1 or to both?

Thanks, Eran

Got no reply, Eran