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PCM5121 pop noise suppression while make internal PLL clock change intentionally

Ericksen Chow
Prodigy 30 points
Other Parts Discussed in Thread: PCM5121

Hi, all,

I m having a project try to make use of PCM5121 DAC capability of pop noise suppression, the details as below.

A SOC act as USB-DAC bridge to receive audio frames from USB device which support standard audio class, pcm5121 convert 44.1Khz sampling rate audio frames to analog. pcm5121 is drived from an external input clock 11.2896M and work as master to provide BCK/LRCK to SOC.  to sync with USB device's frame rate, pcm5121 shall be dynamically controlled to adjust internal PLL output clock, through many small steps of sampling rate fine tune, to get the result DAC convertion rate LRCK change in a range for example 44.0-44.2Khz(BCK simultaneously) to avoid frame buffer overrunning or underrunning. the PLL clock control shall be through three parameters K R P.

The question here try to get help is, can pcm5121 be able to keep working perfectly(means no noise generated out) while  K R P changing to adjust sampling rate on the fly(dynamically)?

From the spec pcm5121 does support MUTE if it detects clock jitter or some else condition, but the I do not hope the MUTE disturb audio at the clock adjust time, because the adjust is awlays happen, several times per second.

Thanks

Ericksen

  • 0
    TI__Genius 16270 points

    Ericksen,

    It is usually not recommended to dynamically change sampling frequency for our DACs and when sampling frequency is changed instantaneously performance cannot be guaranteed.  If sampling frequency is going to be changed, a mute would be recommended. If LRCK changes from 44 to 44.2Khz for example that also may be interpreted as jitter.  Also the MUTE can be adjusted in the registers, so you can control when exactly it is enabled.

  • 0 in reply to Patrick Galvin
    Prodigy 30 points

    Patrick,

    Thanks for you quick reply.

    Its understandable that any DAC always expect stable clock for running. I still try to get confirm if this dac can do better than others while slightly change K R P paramaters, would you mind my go into more details of this chip?

    The 1st question here is, is there an internal unit for the jitter 'detector' after PLL stage? can it be disabled?

    On the other hand, any clock source may have jitter naturally, even a crystal with 50ppm tolerance, cycle by cycle is not exact same, so 2nd question, how much of clock change the 'detector' think an error is coming and manage to MUTE actively?

    Assume a crystal 12Mhz clock feed into pcm5121, enable PLL, PLLCKIN=12M,R=1,K=7.5264,P=1, we can get Fs = (PLLCKIN * R * K) / (P * 2048) = 44.1Khz.  then, change K=7.5266, Fs can be 44.101Khz, it is 20ppm deviation.  to change the K, only one register page0->R23 shall be re-writed.

    Usually a PLL re-write may cause a short time unlock to lock, the question 3rd here is, does this re-write to pcm5121 introduce a big re-lock cycle therefore active jitter detector? if the answer is not absolutely yes, the PLL seems can do good job(hope PLL output continuous clock, no break ), this chip can be used in our project. since no chip to do test so expect TI engineer help to verify this point on the evaluation board, so 4th question, is it possible to check in your labs?  

    Thanks

    Ericksen

  • 0 in reply to Ericksen Chow
    Prodigy 10 points

    Hi Ericksen,

    Did you get sucsess in PLL on the fly re-writing?

    Thank you.

  • 0 in reply to sergey sokolov
    Prodigy 30 points

    Hi,

    It was at that time waiting some comfirm to make the chip could be used in our player but got no reply, since no more useful info in datesheet and we did not have evaluation board to try to find details, we have to change to another one. thanks for your tracking this issue.

    Regards

    Ericksen