I am attempting to use the AIC3204 EVM with the Spectrum Digital OMAP-L137 EVM. I am having problems getting the 3204 codec setup and operating properly. For my application, the AIC3204 will act as a master, generating the WCLK and BCLK for the OMAP McASP.
I believe that I have these two devices connected properly. I have verified that they are communicating correctly via I2C. I have verified using a scope that the OMAP is issuing all of the proper setup commands to the 3204, and that the 3204 is acknowledging the commands. Furthermore, I have read back the register settings to verify that they are being set correctly. The problem comes as the codec goes to turn on the DAC and ADC. When this happens, there is an initial transition of the WCLK, but then the clock just holds high. The codec does not start generating the BCLK and WCLK as it is setup to do. The only issue I can see is that when you read back the status registers in the codec, it is reporting that the gains are not being applied properly. Registers 36 and 37 of page 0 are reporting 0x44 and 0x88, respectively. This indicates that the Left and Right ADC are powered up, the Left and Right DAC are powered up, and LOL and LOR is powered up. However, the registers are indicating that the applied gains do not equal the programmed values for the ADC PGA and the DAC PGA . I do not know whether or not this is causing the codec to fail to start.
I did spend time trying to test just the DAC, and I still couldn't get that to work. I even inserted a while statement that would wait until the applied gains equaled the program gains prior to turning on the DAC. This doesn't seem to make a difference. Finally, I did test these settings with the EVM to make sure the codec ran properly. I was able to sample and output a sine wave from a function generator with these settings.
Any help would be greatly appreciated in setting up this device.
Below is the setup of the codec registers:
// PLL Not used. MCLK is 24.576 MHz clock from function generator. Configured for 96kHz operation for both ADC and DAC, 32-bit, I2S
// EVMOMAPL137_AIC3204_rset( 4, 0x03 ); // Clock Multiplexers <- [CODEC_CLKIN = PLL_CLK]
// EVMOMAPL137_AIC3204_rset( 5, 0xA1 ); // PLL Setup <- [PLL=ON][P=2][R=1]
// EVMOMAPL137_AIC3204_rset( 6, 0x04 ); // PLL Setup J vals <- [J=4]
// EVMOMAPL137_AIC3204_rset( 7, 0x00 ); // PLL Setup D val (MSB) <- [D=0]
// EVMOMAPL137_AIC3204_rset( 8, 0x00 ); // PLL Setup D val (LSB) <- [D=0]
EVMOMAPL137_AIC3204_rset( 11, 0x81 ); // NDAC Divider <- [NDAC=On][NDAC=1]
EVMOMAPL137_AIC3204_rset( 12, 0x82 ); // MDAC Divider <- [MDAC=On][MDAC=2]
EVMOMAPL137_AIC3204_rset( 13, 0x00 ); // DAC OSR Setting (MSB) <- [DOSR_MSB=00]
EVMOMAPL137_AIC3204_rset( 14, 0x80); // DAC OSR Setting (LSB) <- [DOSR_LSB=128]
EVMOMAPL137_AIC3204_rset( 18, 0x81 ); // NADC Divider <- [NADC=On][NADC=2]
EVMOMAPL137_AIC3204_rset( 19, 0x82 ); // MADC Divider <- [MADC=On][MADC=2]
EVMOMAPL137_AIC3204_rset( 20, 0x80 ); // AOSR Setting <- [AOSR=128]
EVMOMAPL137_AIC3204_rset( 27, 0x3C ); // Analog Interface Setting 1 <- [MODE=I2S][Data=32bit][BCLK=Master][WCLK=Master]
EVMOMAPL137_AIC3204_rset( 28, 0x01 ); // Analog Interface Setting 2 <- [Offset=1bit]
EVMOMAPL137_AIC3204_rset( 60, 0x08 ); // DAC Signal Proc Block <- [PRB=8]
EVMOMAPL137_AIC3204_rset( 61, 0x01 ); // ADC Signal Proc Block <- [PRB=1]
EVMOMAPL137_AIC3204_rset( 68, 0x00 ); // DRC Control Register 1 <- [DRC off]
EVMOMAPL137_AIC3204_rset( 69, 0x00 ); // DRC Control Register 2 <- [Disabled]
EVMOMAPL137_AIC3204_rset( AIC3204_PAGESELECT, 1 ); // Select page 1
EVMOMAPL137_AIC3204_rset( 1, 0x08 ); // Power Config <- [Weak AVDD_DVDD=Disabled]
EVMOMAPL137_AIC3204_rset( 2, 0x00 ); // LDO Control Register <- [DVDD=1.72V][AVDD=1.72V][Analog=On][AVDD=Off]
EVMOMAPL137_AIC3204_rset( 3, 0x00 ); // Playback Config 1 <- [LDAC_PTM=PTM_P3,PTM_P4]
EVMOMAPL137_AIC3204_rset( 4, 0x00 ); // Playback Config 2 <- [RDAC_PTM=PTM_P3,PTM_P4]
EVMOMAPL137_AIC3204_rset( 61, 0x00 ); // ADC PowerTune <- [ADCPTM=PTM_R4]
EVMOMAPL137_AIC3204_rset( 71, 0x32 ); // Reference Fast Charging <- [Fast Power up]
EVMOMAPL137_AIC3204_rset( 123, 0x01 );// Reference Fast Charging <- [Power up = 40ms]
EVMOMAPL137_AIC3204_rset( 10, 0x00 ); // Common Mode Control <- [Full Chip CM=0.9V][LOL,LOR=Full Chip CM]
EVMOMAPL137_AIC3204_rset( 14, 0x08 ); // LOL Routing <- [LOL=LDAC]
EVMOMAPL137_AIC3204_rset( 15, 0x08 ); // LOR Routing <- [LOR=LDAC]
EVMOMAPL137_AIC3204_rset( 52, 0x80 ); // Left MICPGA Pos Term Routing <- [LeftMICPGA_P=IN1L,20k]
EVMOMAPL137_AIC3204_rset( 54, 0x80 ); // Left MICPGA Neg Term Routing <- [LeftMICPGA_N=CM1L,20k]
EVMOMAPL137_AIC3204_rset( 55, 0x80 ); // Right MICPGA Pos Routing <- [RightMICPGA_P=IN1R,20k]
EVMOMAPL137_AIC3204_rset( 57, 0x80 ); // Right MICPGA Neg Routing <- [RightMICPGA_N=CM1R,20k]
EVMOMAPL137_AIC3204_rset( 59, 0x0C ); // Left MICPGA Volume <- [Left MICPGA Gain = 6dB?]
EVMOMAPL137_AIC3204_rset( 60, 0x0C ); // Right MICPGA Volume <- [Right MICPGA Gain = 6dB?]
EVMOMAPL137_AIC3204_rset( 18, 0x3B); // LOL Driver Gain <- [Mute=OFF][Gain=0dB]
EVMOMAPL137_AIC3204_rset( 19, 0x3B ); // LOR Driver Gain <- [Mute=OFF][Gain=0dB]
EVMOMAPL137_AIC3204_rset( 9, 0x0C ); // Output Driver Power <- [LOL=On][ROL=On]
// Read register 63 and wait until LOL and LOR applied gain equal to programmed gain
while( (reg2[0] & 0x30) == 0 )
{
EVMOMAPL137_AIC3204_rset( 62, 0x00 ); // Move to Reg 62 prior to read
EVMOMAPL137_I2C_read ( CODEC_ADDR, reg2, 1 ); // Read Reg 62 into reg2
}
EVMOMAPL137_AIC3204_rset( AIC3204_PAGESELECT, 0 ); // Select page 0
EVMOMAPL137_AIC3204_rset( 81, 0xC0 ); // ADC Channel Setup <- [LADC=On][RADC=On][Soft-Step=Off]
EVMOMAPL137_AIC3204_rset( 82, 0x00 ); // ADC Fine Gain Adjust <- [LADC Mute=Off][RADC Mute=Off]
EVMOMAPL137_AIC3204_rset( 65, 0x00 ); // Left DAC Volume <- [LDAC Vol = 0dB]
EVMOMAPL137_AIC3204_rset( 66, 0x00 ); // Right DAC Volume <- [RDAC Vol = 0dB]
EVMOMAPL137_AIC3204_rset( 63, 0xD6 ); // DAC Channel Setup 1 <- [LDAC=On][RDAC=On][LDAC=LData][RDAC=RData][Soft-Step=Off]
EVMOMAPL137_AIC3204_rset( 64, 0x00 ); // DAC Channel Setup 2 <- [LDAC Mute=Off][RDAC Mute=Off]
