MiniDSP interpolation and decimation

Hi, Jim,

I apologize for the delay. Did you get this sorted out already?

-d2

Don,

No, I still don't know the answer to this.

The 8x4x label in a PPS codec framework refers to the miniDSP MAC interpolation and decimation ratios. The corresponding registers are in page 0, register 17 and 23 and have a range of 1 to 16. It is not possible to select a 128x ratio for the miniDSP MAC blocks.

If you want to use 128x oversampling for the ADC and DAC, you can program this separately with the DOSR and AOSR settings. PPS uses an OSR of 128 for the 8x4x framework. Here is the excerpt from the PPS AIC3254 8x4x framework system settings code (you can view the full code in the framework's properties window in PPS):

%%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000)
...
reg[ 0][ 13] = 0x00 ; DOSR = 128 (MSB)
reg[ 0][ 14] = 0x80 ; DOSR = 128 (LSB)
...
reg[ 0][ 20] = 0x80 ; AOSR = 128
...
%%endif

Thank you for that information- it's very helpful.  What exactly does programming the DOSR and AOSR to 128 do?  It clearly changes the sampling clock, but does it cause any kind of anti-aliasing filtering to happen?  If not, doesn't that mean that a lot of noise gets folded in on the ADC side, and a lot of aliased images appear on the DAC side?

Also, how does the miniDSP MAC decimation/interpolation correspond with the clock distribution tree shown in Figure 5-40 of the data sheet?  Does it correspond to MDAC/MADC, or is that still set by page 0 registers 18 and 19?

Regarding my earlier question about AOSR/DOSR, I'm guessing that it doesn't have anti-aliasing filtering, that we would have to handle anti-aliasing filtering external to the chip.  Is this correct?

One last question- it appears to me that PurePath verifies that we have enough clock cycles to do the processing shown in the design drawing.  If we change the MAC decimation/interpolation from what PurePath does (and I'm totally fine with doing that) we lose that check- i.e. we may exceed the number of available clock cycles and not know it.  Is there a way to determine if we have enough clock cycles to do what we want to do or not?

The converter architecture delta-sigma oversampling, which is based on the theory that sampling a signal at much higher rates than necessary (much higher than 2x fmax), the quantization noise will be spread over the much higher bandwidth resulting in increased effective resolution. As a side effect, anti-aliasing requirements are much relaxed because if the converter internally samples at 128x  2xfmax, you can simply add a first order filter (e.g. RC) with a cutoff frequency of for example1.5fmax at the inputs which will remove any high frequency components that may alias back to frequencies below fmax (only f>128x fmax will alias back).

Likewise, on the DAC side you'll get significant out of band noise but because it is much higher than fmax, it's easy to filter with a simple first order filter. The noise is not evenly distributed but shaped way out of band so filtering is simple.