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AIC3254: How to decide the optimal settings for AIC clocks for my process signal flow?

Kaka
Guru 24520 points

Hi community member,

Please let me confirm the way to decide the best setting of AIC clock wiht using my process singal flow. I know that the way has already been described in Technical Reference manual.  But, please let me confirm this, just in case.  Please see the captured screen as below.



I would like to decide the best setting of PLL for this situation by using ACI3254 Control Software(CS). From this captured screen, it seems that the "IADC" or "IDAC" is 529 or 372. Is this right?
If yes, should I type this value in the block of "IADC/IDAC" in PLL Calculator?
* I entered those values to PLL calculator  and attached the result as below. Would you please check whether there is any problem for AIC settings?

Best regards.

Kaka

  • 0
    TI__Guru**** 189401 points

    Hi, Kaka,

    Sorry, we missed your post. Did you get this resolved?

    -d2

  • 0 in reply to Don Dapkus
    Guru 24520 points

    Hi Don,

    I have not gotten the solution for this.

    Would you please explain the way how to set the PLL settings?

    Best regards.

    Kaka

  • 0
    TI__Genius 12255 points

    Hi Kato:

                  You can find the IADCand IDAC in PPS.

                   Click the franwork-->SystemSettingCode, in the souce code, you can find the IADC and IDAC's meaning.

     

          And you should type this value in the block of "IADC/IDAC" in PLL Calculator, if you will use MiniDSP.

            

  • 0 in reply to Derek Xie
    Guru 24520 points

    Hi Dreak,

    Thank you for response.

    However, I have a concern for changing the value of IDAC/IADC by using the script file.  If change those values in manual, the resources of miniDSP may not match with the signal flow.

    So, I think that should confirm whether those values can pass the build with changing those values at "miniDSP_A/D_cycle" on the Framework .

    If can pass it, input this value to IDAC/IADC parameter on  PLL calculator.  Is my understanding correct?

    And I have other concern.

    Is there any influence for the device operation to change this value?

    I would like to know the influence for device in case of changing them.

    Best regards.

    Kaka

  • 0 in reply to Kaka
    TI__Genius 12255 points

    Hi Kato:

                  The PPS will not change the PLL divider. It just download the default one in script.

                   You can see the picture below:  

                    

         The red block is the miniDSP download's IADC and IDAC. The value you should write in PLL calculate.

           The maximum cycle is 50MHz/sample rate. If you sample rate is 48KHz, the maxium cycle is about 1024. 

             The lower cycle means lower power. If your process flow is using a little cycle, you can decrease the value.