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DAC oversampling problem with TLV320AIC3204

Michal Krestan
Prodigy 30 points
Other Parts Discussed in Thread: TLV320AIC3204

 

I've a problem when setting DOSR value of TLV320AIC3204. I can't set any other value than 0x40, otherwise the output of DAC doesn't work. When I have this value set to 0x40, my sample rate is 16kHz, but I want to decrease it to 8kHz. When I change the DOSR value to 0x80, it doesn't work. Can anyone help me? Setting MCLK to half of the frequency doesn't help, because it will produce audible noise to the output i case of 8kHz fs.

 

    Michal

  • 0
    Genius 4530 points

    Hi Michal,

    The audio codec can be used in both Master and Slave mode.

    When in Master mode, it generates its own WCLK and BCLK from its internal PLL.

    But when in Slave mode, the WCLK and BCLK is provided by the Master which can be a DSP processor.

    Changing the WCLK from the Master side, can help you set the Fs to half your present value.

    Hope this helps,

    Regards,

    Sid

  • 0 in reply to Sid
    Prodigy 30 points

     

    This will not help to solve my problem. DOSR will be all the time 0x40 and it's not enough to move the noise produced by DAC out of band, which you can hear. This is only for 8kHz sample rate. I need to know, how to change DOSR to 128 or higher value and let the DAC run. It seems to be a problem with processing block. I'm using PRB_P8, but what's wrong with setting DOSR to 128?

    Michal

  • 0
    TI__Mastermind 46195 points

    Hello Michal,

    When operating a sigma-delta DAC, care must be taken to ensure that the out-of-band noise falls as far as possible from the audible frequency range. Noise might be audible if the oversampling rate of the converter is too low, which might be the case for 8kHz sampling. The optimal DAC oversampling frequency for the AIC3204 is around 6MHz (or 48kHz*128). In order to achieve such oversampling rate for 8kHz sampling, the DOSR must be set to 768.

    The images below show an example taken from AIC3204 CS, where MCLK is 4.096 MHz. Other MCLK frequencies can be used as well, although lower MCLK frequencies might be better suited for host processors that derive its BCLK from MCLK -- which results in less audio time slots per WCLK cycle if a BCLK division factor is limited to a certain amount.

    The values for MDAC and MADC below are chosen to be compatible with all processing blocks as well as miniDSP programs for AIC3254. This may not be the optimal values from a power consumption standpoint -- once a processing block is seleted for you system (say, only 3 biquads are needed per channel, as for PRB_P1 which has a resource class (RC) of 8) the MDAC and NDAC values can be tuned for that particular resource class. Please refer to http://focus.ti.com/lit/an/slaa404b/slaa404b.pdf for further details. Page 20 has a sample script related to 8kHz sampling.

     

    Regards,

    J-

     

     

     

     

     

  • 0 in reply to J-
    Prodigy 30 points

    Please could anybody tell me or give me some script for configuring DAC with DOSR>=128? I've tried to use sample script from TLV320AIC3204 datasheet, however it doesn't work with fs=8kHz and DOSR with different value than 64 (I've tried 768, or 128). I only need to modify it for my I2S interface, where I need to have CODEC as master and I'm using PLL to generate MCLK from external clock, which are running at 900kHz. I looks like it's a problem with selected processing block, however I've tried 3 different PB and the result was the same. Only it has changed the output form silent to loud noise, or it has stopped generating clock on I2S.

  • 0 in reply to Michal Krestan
    TI__Mastermind 46195 points

    Michal,

    Please refer to page 83 of http://focus.ti.com/lit/ds/symlink/tlv320aic3204.pdf. To derive 8 kHz from a 900 kHz, a fractional divider would be needed (for OSR >= 128). This means that divider D would be different than 0. For such a case, PLL_CLKIN / P must be higher than 10 MHz.

    I suggest the following solutions:

    1. Obtain a higher clock that does not require use of the fractional divider (e.g. 4.096 MHz, 12.288 MHz, etc.) or a clock that is higher than 10 MHz, or
    2. Configure the AIC3204 as a slave and use BCLK as the source for PLL_CLKIN to generate its internal MCLK.

    Regards,

    J-