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Max WDCK frequency in PCM1794A External DF mode?

Wayne14475
Prodigy 30 points

Other Parts Discussed in Thread: PCM1794A

I have a question regarding PCM1974A datasheet. Is the internal digital filter running at 8x oversampling ratio even at the maximum input sampling rate fs of 200KHz? The oversampled signal rate between the digital filter and the multi-level sigma-delta modulator would then be 1.6MHz. High performance audio DACs from other companies seem to run at lower oversampling ratios at high input sampling rates, so that the output rate of the oversampling filter is kept relatively constant. A somewhat related question is whether the maximum fs of 200KHz also applies to the external digital filter mode, where the frequency of WDCK can be either 4fs(800KHz) or 8fs (1.6MHz). If not, what is the upper limit for WDCK frequency in external digital filter mode? Thank you.

  • 0
    TI__Expert 4625 points

    Wayne,

    Yes, the 8x oversampling ratio applies to the entire sampling frequency range of 10kHz to 200kHz.

    And yes, when operating with an external digital filter, the frequency of WDCK can be a maximum of either 800kHz (4fs) or 1.6MHz (8fs)

    Regards,

    Nick

     

  • 0 in reply to Nick
    Prodigy 30 points

    Nick,

    Thanks a lot for your reply.

    Another related question, does PCM1794A automatically adjust its multi-level sigma-delta modulator oversampling ratio base on different input sampling rates, or it is fixed at 8x or 4x? (16x oversampling would require a 256fs or higher system clock, which is not enforced on PCM1794A) .

    We found that when WDCK=768KHz, the system clock has to be above 24.576MHz for PCM1974A to function properly. There seems to be a clock frequency requirement related to the oversampling ratio of the sigma-delta modulator not explicitly specified in the datasheet.

    Thank you.

    Wayne

  • 0 in reply to Wayne14475
    TI__Expert 4625 points

    Wayne,

    I agree--the relationship is not explicitly stated.

    Since this is dependent on the internal clocking circuitry, I'm going to run this by our design team first and then get back with you.

    Nick

  • 0 in reply to Wayne14475
    TI__Expert 4625 points

    Hi Wayne,

    In the PCM1794A, the delta sigma modulator oversampling rate is fixed at 8x (modulator oversampling) * 8x (filter oversampling) = 64fs.  With an external filter, this can be 64fs or 32fs, depending on whether the filter is 8x or 4x oversampling.

    768kHz is 4x the data rate of a 192kHz fs.  With an fs of 192kHz, the minimum system clock that can be used is 24.576MHz, according to table 1 of the datasheet.

    Regards,

    Nick

     

  • 0 in reply to Nick
    Prodigy 30 points

    Hi Nick,

    Thanks for your reply, I got the information I needed.

    However I don't think table 1 in the datasheet applies to the external DF configuration, because PCM1794A has no knowledge about the PCM sampling rate at the input of the external DF.  A 768KHz WDCK could either mean 4fs@192KHz or 8fs@96KHz PCM input. According to table 1, the minimum system clock frequency would be 24.576MHz or 12.288MHz. Apparently there is only one system clock lower limit that is 24.576MHz.

    Regards,

    Wayne

  • 0 in reply to Wayne14475
    Prodigy 20 points

    Closely related to the above questions is, what is the MINIMUM LRCK frequency which can be applied to the PCM1794A set in external digital filter mode? Is the issue actually the LRCK frequency, or rather some minimum SCK frequency which must by applied?

    My application features a custom digital filter implementation which would provide samples eather at a 1Fs or 2Fs LRCK rate to the DAC, not the 4x or 8x specified in the PCM1794A data sheet.

    Thanks, in advance, to whoever can provide an accurate answer.

  • 0 in reply to Ken Newton
    Prodigy 20 points

    Please forget my above question. I've since found the answer.