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PurePath & AIC3254

Matthew Osborne
Prodigy 110 points

I am using the PurePath GDE with an AIC3254.

My process flow uses the AIC3254App8x4x framework and mixes the left and right ADC channels onto the left I2S channel by routing from a Dec4xIn to a Mono_Mixer and finally to a MonoI2S_Out component.

I've noticed that the configuration script that's generated when I build my process flow contains quite a bit of boilerplate configuration values (for use with the evaluation kit).

I've changed the clocking, input routing and ADC settings to match my hardware, but I am curious as to why the script is generating DAC instructions and coefficients? I don't think my process flow makes use of the DAC miniDSP, do I need to include them anyway?

The DAC/ADC Signal Processing Block Control registers don't have the same control options for the DAC/ADC miniDSPs either. Is it possible to only use the ADC miniDSP and leave the DAC miniDSP powered down? Do both ADC channels have to be powered up for the ADC miniDSP to operate, and is it possible to power on/off the left/right ADCs (but not have both off at the same time) and still have the ADC miniDSP function?

 

Thanks,

Matt.

 

  • 0
    Prodigy 110 points

    It appears that either the left or right ADC can be powered up/down without stopping the ADC miniDSP. I was having problems (clocking was wrong) but have sorted them out...

    I think these values are correct - the miniDSP runs okay.

    I have the following input clocks: MCLK of 12 MHz, BCLK of 256 kHz, and WCLK of 8kHz.

    For an ADC_FS of 8kHz and AOSR = 128 I have the following divider settings: NADC=2, MADC=8.

    My CODEC_CLK is derived from the MCLK via the PLL with the following settings: R=1, P=3, J=4, D=0960.

    I hope these values are sufficient and appropriate - there weren't any example settings for 12MHz with an 8kHz sample rate in the data sheet. Any feedback would be appreciated.

     

  • 0 in reply to Matthew Osborne
    Prodigy 110 points

    From http://e2e.ti.com/forums/t/8846.aspx

    MADC*AOSR > IADC (if ADC or interporcessor component is used)

    I'm good with by IADC of 904!

  • 0 in reply to Matthew Osborne
    TI__Mastermind 46195 points

    Hi Matthew,

    Either miniDSP is powered up if at least one of the converters is powered up. For example, if LADC is powered, then miniDSP_A will be powered. If LADC and RADC are powered off, then the miniDSP_A will be powered down. Unless there is an interprocessor component being used, there is no need to power the miniDSP_D (or DACs) if only miniDSP_A is used.

    Below are clock settings for 8kHz sampling using a 12 MHz master clock, AIC3254 is a slave. For your reference, I also included the DAC dividers MDAC and NDAC as well as DOSR. You can remove those lines if not used. Note the EVM does not work with the settings below (i.e. MCLK is not 12MHz). Refer to the PurePath Studio GDE documentation for detais on the EVM's clocking scheme / sampling rates.

    ###############################################
    # Clock and Interface Settings
    # ---------------------------------------------
    # The codec receives: MCLK = 12 MHz,
    # BLCK = 512 kHz, WCLK = 8 kHz
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # PLL_clkin = MCLK, codec_clkin = PLL_CLK,
    # PLL on, P=1, R=1, J=8, D=1920
    w 30 04 03 91 08 07 80
    #
    # NDAC = 2, MDAC = 8, dividers powered on
    w 30 0b 82 88
    #
    # DOSR = 768
    w 30 0D 03 00
    #
    # NADC = 12, MADC = 8, dividers powered on
    w 30 12 8C 88
    #
    # AOSR = 128
    w 30 14 80
    #
    ###############################################

     

    Regards,

    JA

  • 0 in reply to J-
    Prodigy 110 points

    Thanks for the values - they seem to result in better quality audio than the ones I was using!

    In the following post:

    http://e2e.ti.com/forums/t/8073.aspx

    it is mentioned that BCLK needs to be fast enough to get all of the bits during the current sample.

    Is there a rule to ensure that this is the case (similar to MADC*AOSR > IADC). My BCLK and WCLK are not sync'd to the MCLK either.

    Thanks again,

    Matt.

     

  • 0 in reply to Matthew Osborne
    TI__Mastermind 46195 points

    Hi Matthew,

    Good question!

    1) BCLK and WCLK (I2S bus) must be synchronized with each other. It must be at least (16 bits)*(2 channels)*WCLK and must latch the data as specified in the I2S timing diagram of the datasheet.

    2) MCLK does not need to be synchronized to any edge or position relative to the I2S bus. However, when the MCLK get divided down to the sampling frequency, it should not be too fast or too slow compared to the I2S bus, otherwise you might have missed or repeated samples. An exaggerated case is if the clock dividers are set for 44.1kHz sampling but the I2S bus is operating at 22.05kHz sampling. This would result in duplicate samples through the I2S bus DAC data.

    3) The above does not apply if the AIC3254 is the I2S master, since I2S is derived from MCLK.

    Regards,

    JA