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TLV320AIC32 input clocks

Other Parts Discussed in Thread: TLV320AIC32

Regarding the MCLK,BCLK,WCLK when configured as inputs and considering BCLK and WCLK are in-phase, does a phase difference between MCLK and BCLK(or WCLK) has any effect on the audio?

  • The actual sample rate is set by MCLK and the PLL or divider ratios selected in the registers. WCLK and BCLK are simply used to clock (and in) the data. It is important that WCLK is an exact multiple of MCLK and is at the sample rate. If MCLK fast or slow, you will re-clock the same data or miss samples. The exact phase relationship is not critical. BCLK just needs to be fast enough to get all of the bits during the current sample.

  • Hello,

    I want to connect the TLV320AIC32 on a raspberry PI. The raspberry PI have a PCM interface (on the connector P5).

    My question is how to connect MCLK, BCLK, WCLK, DIN and DOUT on the PCM interface of the raspberry (PCM_CLK, PCM_FS, PCM_DIN and PCM_DOUT) ?

    Thank you.