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TLV320AIC26 Codec clocking slip question

P Oliver
Prodigy 10 points


Hello,

I'm looking for more info on how this codec handles slip between its I2S data bus and the ADC/DAC when the chip is in I2S slave mode. From what I read in the datasheet, the sample rate of the ADC/DAC is configured through register settings and is derived from the MCLK input using an internal PLL. If the I2S stream LRCLK is derived from a clock source other than the one that feeds the MCLK pin but is matched (within approx 200ppm), how will the DAC handle the frame slip if the LRCKL is faster/slower than the internal Fs? Will it repeat the previous sample? Will it output a 0V blip?

Please advise. Thanks!

 

 

  • 0
    TI__Mastermind 46195 points

    Hello Oliver,

    If the external WCLK/BCLK slips, you might expect data being repeated or missed. If the external BCLK and WCLK are expected to vary significantly with respect to the codec's internal sampling, it might be best to configure the AIC26 as an I2S master (if the host supports slave mode).

    Regards,

    JA